CSEE 4840 - Spring 2008 - 128-bit AES decryption - Final ReportABSTRACT1. INTRODUCTION2. HARDWARE DESIGN2.0 Hardware overview2.1 AES decrypto2.1.1 Algorithm2.1.2 Optimized Hardware Design2.1.3 Timing2.2 SD-card SPI interface2.2.1. MMC/SD Card Pin Assignments in SPI Mode2.2.2. SPI Commands2.2.3. SPI Clock Control2.2.4. Mode Selection2.2.5. Initialization Sequence2.2.6. Data Read2.2.7. Implementation2.3 VGA and SRAM controller2.3.1 VGA implementation2.3.2 SRAM implementation2.4 LCD Display and Keyboard2.5 Resource consumption3. SOFTWARE DESIGN4. RESULTS5. Task division6. Lessons Learned7.Advice for Future Students8. Acknowledgments9. REFERENCESAbout the authorsAPPENDICESC codeprojectv3v2aesenv2aesdecv2keyboard_hv2keyboard_cv2VHDL codetoplevelaes128_niosAES_decryptocontrollerdemux1_2expansion_keysgenerate_roundkeyinv_addroundkeyinv_mixcolumnsinv_mtimesinv_multiplyinv_multiply_rowinv_sboxinv_shiftrow_subbyteskey_controllermux128_1regis128sboxwrite_controllerspi_controllervga_sram_supercontrollerde2_vga_rasterde2_sram_controllerCSEE 4840 Project Report – May 2008 CSEE 4840 Shrivathsa Bhargav Larry Chen Abhinandan Majumdar Shiva Ramudit CSEE 4840 – Embedded System Design Spring 2008, Columbia University 128-bit AES decryption128-bit AES decryption Project report CSEE 4840, Spring 2008, Columbia University 2 Table of Contents ABSTRACT ............................................................................................................................................... 3 1. INTRODUCTION ................................................................................................................................. 3 2. HARDWARE DESIGN .......................................................................................................................... 3 2.0 Hardware overview ...................................................................................................................... 3 2.1 AES decrypto ............................................................................................................................... 4 2.1.1 Algorithm .............................................................................................................................. 4 2.1.2 Optimized Hardware Design .................................................................................................. 6 2.1.3 Timing ................................................................................................................................... 6 2.2 SD-card SPI interface ................................................................................................................... 7 2.2.1. MMC/SD Card Pin Assignments in SPI Mode ......................................................................... 7 2.2.2. SPI Commands...................................................................................................................... 7 2.2.3. SPI Clock Control .................................................................................................................. 8 2.2.4. Mode Selection .................................................................................................................... 8 2.2.5. Initialization Sequence.......................................................................................................... 8 2.2.6. Data Read ............................................................................................................................. 8 2.2.7. Implementation.................................................................................................................... 8 2.3 VGA and SRAM controller ............................................................................................................ 9 2.3.1 VGA implementation ............................................................................................................ 9 2.3.2 SRAM implementation........................................................................................................ 10 2.4 LCD Display and Keyboard ......................................................................................................... 10 2.5 Resource consumption .............................................................................................................. 10 3. SOFTWARE DESIGN ......................................................................................................................... 10 4. RESULTS .......................................................................................................................................... 11 5. TASK DIVISION ................................................................................................................................ 11 6. LESSONS LEARNED .......................................................................................................................... 11 7. ADVICE FOR FUTURE STUDENTS ...................................................................................................... 11 8. ACKNOWLEDGMENTS ..................................................................................................................... 11 9. REFERENCES.................................................................................................................................... 11 ABOUT THE AUTHORS ........................................................................................................................... 11 APPENDICES128-bit AES decryption Project report CSEE 4840, Spring 2008, Columbia University 3 FPGA-based 128-bit AES decryption Shrivathsa Bhargav, Larry Chen, Abhinandan Majumdar, Shiva Ramudit {sb2784, lc2454, am2993, syr9}@columbia.edu ABSTRACT The original objective of the AES project was to create an AES decryption system for images. The end result has exceeded the original objective and the AES group designed and implemented an FPGA-based high-speed 128-bit AES decryption system for 6 fps “video” comprised of sequential images. The images are pre-encrypted, and are read as .BMP files from an SD-card. 1. INTRODUCTION The Advanced Encryption Standard (AES, also known as Rijndael) [1] is well-known
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