Combinational Procs.: SensitivityAlways assign all outputsAccidental Level-Sensitive Latches``Default'' values are convenientFSMs: Leave out default for helpSeq. Processes: SensitivitySeq. Processes: Avoid AsyncSimulation: One version onlyDon't Add Ficticious I/OStick to the Synchronous ModelCristian’s Rules for Good VHDLProf. Stephen A. [email protected] UniversitySpring 2006Cristian’s Rules for Good VHDL – p. 1/11Combinational Procs.: SensitivityList all process inputs in the sensitivity list.process (current_state, long)beginif (reset = ’1’) thennext_state <= HG;start_timer <= ’1’;elsecase current_state iswhen HG =>farm_yellow <= ’0’;if (cars = ’1’ and long = ’1’) thennext_state <= HY;elsenext_state <= HG;end if;when HY =>farm_yellow <= ’0’;if (short = ’1’) thennext_state <= FG;elsenext_state <= HY;end if;process (current_state, reset, cars, short, long)beginif (reset = ’1’) thennext_state <= HG;start_timer <= ’1’;elsecase current_state iswhen HG =>farm_yellow <= ’0’;if (cars = ’1’ and long = ’1’) thennext_state <= HY;elsenext_state <= HG;end if;when HY =>farm_yellow <= ’0’;if (short = ’1’) thennext_state <= FG;elsenext_state <= HY;end if;Cristian’s Rules for Good VHDL – p. 2/11Always assign all outputsSynthesis infers level-sensitive latches otherwise.process (current_state, input)begincase current_state iswhen S1 =>if (input = ’1’) thenoutput <= ’0’;end if;when S2 =>output <= ’1’;end case;end process;process (current_state, input)begincase current_state iswhen S1 =>if (input = ’1’) thenoutput <= ’0’;elseoutput <= ’1’;end if;when S2 =>output <= ’1’;end case;end process;Cristian’s Rules for Good VHDL – p. 3/11Accidental Level-Sensitive LatchesSection from .mrp whenyou have latchesDesign Summary--------------Number of errors: 0Number of warnings: 0Logic Utilization:Total Number Slice Registers: 18 out of 6,144Number used as Flip Flops: 16Number used as Latches: 2Number of 4 input LUTs: 23 out of 6,144Section from .mrp withno latchesDesign Summary--------------Number of errors: 0Number of warnings: 0Logic Utilization:Number of Slice Flip Flops: 31 out of 6,144Number of 4 input LUTs: 16 out of 6,144Cristian’s Rules for Good VHDL – p. 4/11“Default” values are convenient-- OKprocess (current_state, input)begincase current_state iswhen S1 =>if (input = ’1’) thenoutput <= ’0’;elseoutput <= ’1’;end if;when S2 =>output <= ’1’;end case;end process;-- Betterprocess (current_state, input)beginoutput <= ’1’;case current_state iswhen S1 =>if (input = ’1’) thenoutput <= ’0’;end if;end case;end process;Cristian’s Rules for Good VHDL – p. 5/11FSMs: Leave out default for helpBetter to use an enumeration to encode states:type mystate is (START,RUN,IDLE,ZAPHOD);signal cst : mystate;signal nxst : mystate;process(cst)begincase cst iswhen START => ...when RUN => ...when IDLE => ...end case;end process;Running this produces a helpful error:Compiling vhdl file "/home/cristi/cs4840/lab4/main.vhd" in Library work.Entity <system> compiled.ERROR:HDLParsers:813 - "/home/cristi/cs4840/lab4/main.vhd" Line 80.Enumerated value zaphod is missing in case.-->Cristian’s Rules for Good VHDL – p. 6/11Seq. Processes: SensitivityAlways include the clock. Include reset ifasynchronous, and nothing else.process (Clk, D)beginif (Clk’event and Clk = ’1’) thenQ <= D;end if;end process;process (Clk, D)beginif (reset = ’1’) thenQ <= ’0’;elseif (Clk’event and Clk = ’1’) thenQ <= D;end if;end if;end process;process (Clk)beginif (Clk’event and Clk = ’1’) thenQ <= D;end if;end process;process (Clk, reset)beginif (reset = ’1’) thenQ <= ’0’;elseif (Clk’event and Clk = ’1’) thenQ <= D;end if;end if;end process;Cristian’s Rules for Good VHDL – p. 7/11Seq. Processes: Avoid AsyncOnly use asynchronous reset when there is oneglobal signal from outside.-- OK if Reset is from outsideprocess (Clk, Reset)beginif (Reset = ’1’) thenQ <= ’0’;elseif (Clk’event and Clk = ’1’) thenQ <= D;end if;end if;end process;-- Betterprocess (Clk)beginif (Clk’event and Clk = ’1’) thenif (Reset = ’1’) thenQ <= ’0’;elseQ <= D;end if;end if;end process;Cristian’s Rules for Good VHDL – p. 8/11Simulation: One version onlyNever assume signals from the test benchthat are not there on the boardIt is hard enough to make simulation matchthe design; do not make it any harderIf you must slow down hardware, carefullygenerate a slower clock and only use thatclock globally.Cristian’s Rules for Good VHDL – p. 9/11Don’t Add Ficticious I/OPorts on the topmost entity must correspond toFPGA I/O pins and must be defined in the .ucffile.entity system isport (clk : in std_logic;PB_D0, PB_D1, PB_D2, PB_D3,PB_D4, PB_D5, PB_D6, PB_D7,PB_D8, PB_D9, PB_D10, PB_D11,PB_D12, PB_D13, PB_D14, PB_D15: out std_logic);end system;UCF file:net CLK loc="p77";net PB_D0 loc="p153";net PB_D1 loc="p145";net PB_D2 loc="p141";net PB_D3 loc="p135";entity system isport (clk : in std_logic;PB_D0, PB_D1, PB_D2, PB_D3,PB_D4, PB_D5, PB_D6, PB_D7: out std_logic;);end system;UCF file:net CLK loc="p77";net PB_D0 loc="p153";net PB_D1 loc="p145";net PB_D2 loc="p141";net PB_D3 loc="p135";net PB_D4 loc="p126";net PB_D5 loc="p120";net PB_D6 loc="p116";net PB_D7 loc="p108";Cristian’s Rules for Good VHDL – p. 10/11Stick to the Synchronous ModelExactly one value per signal per clock cycleDo not generate asynchronous reset signals;only use them if they are externalEdge-triggered flip-flops only. Nolevel-sensitive logic.Do not generate clock signals. Usemultiplexers to create “load enable” signals onflip-flops.Cristian’s Rules for Good VHDL – p.
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