Writing VHDL for RTL SynthesisStephen A. Edwards, Columbia UniversityDecember 4, 2007The name VHDL is representative of the language itself: it is a two-level acronymthat stands for VHSIC Hardware Description Language; VHSIC stands for very highspeed integrated circuit. The language is vast, verbose, and was originally designedfor modeling digital systems for simulation. As a result, the full definition of the lan-guage [1] is much larger than what we are concerned with here because many con-structs in the language (e.g., variables, arbitrary events, floating-point types, delays) donot have hardware equivalents and hence not synthesizable.Instead, we focus here on a particular dialect of VHDL dictated in part by the IEEEstandard defining RTL synthesis [2]. Even within this standard, there are many equiv-alent ways to do essentially the same thing (e.g., define a process representing edge-sensitive logic). This document presents a particular idiom that works; it does not tryto define all possible synthesizable VHDL specifications.1 StructureMuch like a C program is mainly a series of function definitions, a VHDL specificationis mainly a series of entity/architecture definition pairs. An entity is an object witha series of input and output ports that represent wires or busses, and an architectureis the “guts” of an entity, comprising concurrent assignment statements, processes, orinstantiations of other entities.Concurrent assignment statements that use logical expressions to define the valuesof signals are one of the most common things in architectures. VHDL supports thelogical operators and, or, nand, nor, xnor, xnor, and not.library ieee; -- add this to the IEEE libraryuse ieee.std_logic_1164.all; -- includes std_ulogicentity full_adder isport(a, b, c : in std_ulogic;sum, carry : out std_ulogic);end full_adder;architecture imp of full_adder isbeginsum <= (a xor b) xor c; -- combinational logiccarry <= (a and b) or (a and c) or (b and c);end imp;11.1 ComponentsOnce you have defined an entity, the next thing is to instantiate it as a component withinanother entity’s architecture.The interface of the component must be defined in any architecture that instantiatesit. Then, any number of port map statements create instances of that component.Here is how to connect two of the full adders to give a two-bit adder:library ieee;use ieee.std_logic_1164.all;entity add2 isport (A, B : in std_logic_vector(1 downto 0);C : out std_logic_vector(2 downto 0));end add2;architecture imp of add2 iscomponent full_adderport (a, b, c : in std_ulogic;sum, carry : out std_ulogic);end component;signal carry : std_ulogic;beginbit0 : full_adder port map (a => A(0),b => B(0),c => ’0’,sum => C(0),carry => carry);bit1 : full_adder port map (a => A(1),b => B(1),c => carry,sum => C(1),carry => C(2));end imp;1.2 MultiplexersThe when...else construct is one way to specify a multiplexer.library ieee;use ieee.std_logic_1164.all;entity multiplexer_4_1 isport(in0, in1, in2, in3 : in std_ulogic_vector(15 downto 0);s0, s1 : in std_ulogic;z : out std_ulogic_vector(15 downto 0));end multiplexer_4_1;architecture imp of multiplexer_4_1 isbeginz <= in0 when (s0 = ’0’ and s1 = ’0’) elsein1 when (s0 = ’1’ and s1 = ’0’) elsein2 when (s0 = ’0’ and s1 = ’1’) elsein3 when (s0 = ’1’ and s1 = ’1’) else"XXXXXXXXXXXXXXXX";end imp;2The with...select is another way to describe a multiplexer.architecture usewith of multiplexer_4_1 issignal sels : std_ulogic_vector(1 downto 0); -- Local wiresbeginsels <= s1 & s0; -- vector concatenationwith sels selectz <=in0 when "00",in1 when "01",in2 when "10",in3 when "11","XXXXXXXXXXXXXXXX" when others;end usewith;1.3 DecodersOften, you will want to take a set of bits encoded in one way and represent them inanother. For example, the following one-of-eight decoder takes three bits and usesthem to enable one of eight.library ieee;use ieee.std_logic_1164.all;entity dec1_8 isport (sel : in std_logic_vector(2 downto 0);res : out std_logic_vector(7 downto 0));end dec1_8;architecture imp of dec1_8 isbeginres <= "00000001" when sel = "000" else"00000010" when sel = "001" else"00000100" when sel = "010" else"00001000" when sel = "011" else"00010000" when sel = "100" else"00100000" when sel = "101" else"01000000" when sel = "110" else"10000000";end imp;1.4 Priority EncodersA priority encoder returns a binary value that indicates the highest set bit among many.This implementation says the output when none of the bits are set is a “don’t-care,”meaning the synthesis system is free to generate any output it wants for this case.library ieee;use ieee.std_logic_1164.all;entity priority isport (sel : in std_logic_vector(7 downto 0);code : out std_logic_vector(2 downto 0));end priority;architecture imp of priority isbegincode <= "000" when sel(0) = ’1’ else"001" when sel(1) = ’1’ else"010" when sel(2) = ’1’ else"011" when sel(3) = ’1’ else"100" when sel(4) = ’1’ else"101" when sel(5) = ’1’ else"110" when sel(6) = ’1’ else"111" when sel(7) = ’1’ else"---"; -- output is a "don’t care"end imp;31.5 Arithmetic UnitsVHDL has extensive support for arithmetic. Here is an unsigned 8-bit adder with carryin and out. By default VHDL’s + operator returns a result that is the same width asits arguments, so it is necessary to zero-extend them to get the ninth (carry) bit out.One way to do this is to convert the arguments to integers, add them, then convert themback.library ieee;use ieee.std_logic_1164.all;use ieee.std_logic_arith.all;use ieee.std_logic_unsigned.all;entity adder isport (A, B : in std_logic_vector(7 downto 0);CI : in std_logic;SUM : out std_logic_vector(7 downto 0);CO : out std_logic);end adder;architecture imp of adder issignal tmp : std_logic_vector(8 downto 0);begintmp <= conv_std_logic_vector((conv_integer(A) + conv_integer(B) +conv_integer(CI)), 9);SUM <= tmp(7 downto 0);CO <= tmp(8);end imp;A very primitive ALU might perform either addition or subtraction:library ieee;use ieee.std_logic_1164.all;use ieee.std_logic_unsigned.all;entity alu isport (A, B : in std_logic_vector(7 downto 0);ADD : in std_logic;RES : out std_logic_vector(7 downto 0));end alu;architecture imp of alu isbeginRES <= A + B when ADD = ’1’ elseA - B;end imp;VHDL provides the usual arithmetic comparison operators. Note that signed andunsigned versions behave differently.library ieee;use ieee.std_logic_1164.all;use ieee.std_logic_unsigned.all;entity comparator
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