Columbia CSEE 4840  Writing VHDL for RTL Synthesis (9 pages)
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Writing VHDL for RTL Synthesis
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 Csee 4840  Embedded System Design
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Writing VHDL for RTL Synthesis Stephen A Edwards Columbia University December 4 2007 The name VHDL is representative of the language itself it is a two level acronym that stands for VHSIC Hardware Description Language V HSIC stands for very high speed integrated circuit The language is vast verbose and was originally designed for modeling digital systems for simulation As a result the full definition of the language 1 is much larger than what we are concerned with here because many constructs in the language e g variables arbitrary events floating point types delays do not have hardware equivalents and hence not synthesizable Instead we focus here on a particular dialect of VHDL dictated in part by the IEEE standard defining RTL synthesis 2 Even within this standard there are many equivalent ways to do essentially the same thing e g define a process representing edgesensitive logic This document presents a particular idiom that works it does not try to define all possible synthesizable VHDL specifications 1 Structure Much like a C program is mainly a series of function definitions a VHDL specification is mainly a series of entity architecture definition pairs An entity is an object with a series of input and output ports that represent wires or busses and an architecture is the guts of an entity comprising concurrent assignment statements processes or instantiations of other entities Concurrent assignment statements that use logical expressions to define the values of signals are one of the most common things in architectures V HDL supports the logical operators and or nand nor xnor xnor and not library ieee use ieee std logic 1164 all add this to the IEEE library includes std ulogic entity full adder is port a b c in std ulogic sum carry out std ulogic end full adder architecture imp of full adder is begin sum a xor b xor c combinational logic carry a and b or a and c or b and c end imp 1 1 1 Components Once you have defined an entity the next thing is to instantiate it as a component within another entity s architecture The interface of the component must be defined in any architecture that instantiates it Then any number of port map statements create instances of that component Here is how to connect two of the full adders to give a two bit adder library ieee use ieee std logic 1164 all entity add2 is port A B in std logic vector 1 downto 0 C out std logic vector 2 downto 0 end add2 architecture imp of add2 is component full adder port a b c in std ulogic sum carry out std ulogic end component signal carry std ulogic begin bit0 full adder port map a A 0 b B 0 c 0 sum C 0 carry carry bit1 full adder port map a A 1 b B 1 c carry sum C 1 carry C 2 end imp 1 2 Multiplexers The when else construct is one way to specify a multiplexer library ieee use ieee std logic 1164 all entity multiplexer 4 1 is port in0 in1 in2 in3 in std ulogic vector 15 downto 0 s0 s1 in std ulogic z out std ulogic vector 15 downto 0 end multiplexer 4 1 architecture imp of multiplexer 4 1 is begin z in0 when s0 0 and s1 0 in1 when s0 1 and s1 0 in2 when s0 0 and s1 1 in3 when s0 1 and s1 1 XXXXXXXXXXXXXXXX end imp 2 else else else else The with select is another way to describe a multiplexer architecture usewith of multiplexer 4 1 is signal sels std ulogic vector 1 downto 0 begin sels s1 s0 with sels select z in0 in1 in2 in3 XXXXXXXXXXXXXXXX end usewith when when when when when Local wires vector concatenation 00 01 10 11 others 1 3 Decoders Often you will want to take a set of bits encoded in one way and represent them in another For example the following one of eight decoder takes three bits and uses them to enable one of eight library ieee use ieee std logic 1164 all entity dec1 8 is port sel in std logic vector 2 downto 0 res out std logic vector 7 downto 0 end dec1 8 architecture imp of dec1 8 is begin res 00000001 when sel 00000010 when sel 00000100 when sel 00001000 when sel 00010000 when sel 00100000 when sel 01000000 when sel 10000000 end imp 000 001 010 011 100 101 110 else else else else else else else 1 4 Priority Encoders A priority encoder returns a binary value that indicates the highest set bit among many This implementation says the output when none of the bits are set is a don t care meaning the synthesis system is free to generate any output it wants for this case library ieee use ieee std logic 1164 all entity priority is port sel in std logic vector 7 downto 0 code out std logic vector 2 downto 0 end priority architecture imp of priority is begin code 000 when sel 0 1 001 when sel 1 1 010 when sel 2 1 011 when sel 3 1 100 when sel 4 1 101 when sel 5 1 110 when sel 6 1 111 when sel 7 1 end imp else else else else else else else else output is a don t care 3 1 5 Arithmetic Units VHDL has extensive support for arithmetic Here is an unsigned 8 bit adder with carry in and out By default VHDL s operator returns a result that is the same width as its arguments so it is necessary to zero extend them to get the ninth carry bit out One way to do this is to convert the arguments to integers add them then convert them back library ieee use ieee std logic 1164 all use ieee std logic arith all use ieee std logic unsigned all entity adder is port A B in std logic vector 7 downto 0 CI in std logic SUM out std logic vector 7 downto 0 CO out std logic end adder architecture imp of adder is signal tmp std logic vector 8 downto 0 begin tmp conv std logic vector conv integer A conv integer B conv integer CI 9 SUM tmp 7 downto 0 CO tmp 8 end imp A very primitive ALU might perform either addition or subtraction library ieee use ieee std logic 1164 all use ieee std logic unsigned all entity alu port A B ADD RES end alu is in std logic vector 7 downto 0 in std logic out std logic vector 7 downto 0 architecture imp of alu is begin RES A B when ADD 1 else A B end imp VHDL provides the usual arithmetic comparison operators Note that signed and unsigned versions behave differently library ieee use ieee std logic 1164 all use ieee std logic unsigned all entity comparator is port A B in std logic vector 7 downto 0 GE out std logic end comparator architecture imp of comparator is begin GE 1 when A …
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