CSEE W4840 Embedded System Design Lab 1Stephen A. EdwardsDue February 9, 2012AbstractLearn to use the Altera Quartus development envrionmentand the DE2 boards by implementing a small hardware designthat displays and modifies the contents of a small memory.1 IntroductionUse the Altera DE2 board to implement a simple hardware de-sign. Describe its behavior using the VHDL language and useAltera’s Quartus tools to synthesize and program the FPGA de-vice. Use a VHDL simulator to verify and debug the design.The circuit you program into the FPGA will display andmodify the contents of a 16 × 8 bit RAM. Although there arededicated RAM chips on the DE2 board, for simplicity use aRAM inside the FPGA. Use four pushbuttons as inputs andthree seven-segment LED displays as outputs. Two push but-tons should step up and down through the sixteen RAM loca-tions; the other two should increment and decrement the con-tents of the currently-displayed memory location. One seven-segment display should show the current address (0–F), twoothers should display the contents of that location in hexadec-imal (00–FF).You will learn to set up a project in the Altera Quartus tool,run a VHDL simulation, and compile and download your de-sign to the FPGA. VHDL is a hardware description language,and the process of using it is very different than developingprograms in C++ or Java. You will need these skills in later labsand while you are developing your project.Below, we introduce the DE2 board, show how to start a newproject from a template, add VHDL code to a project, simulateit, and compile and download a design to the FPGA.2 The DE2 BoardFigure 1 shows the Altera DE2 board. It consists of an AlteraCyclone II FPGA connected to a variety of peripherals includ-ing 512K of SRAM, 4 MB of Flash, 8 MB of SDRAM, VGA out-put, Ethernet, audio input and output, and USB ports. For thislab, we will use four of the eight seven-segment LEDs and thefour blue pushbuttons. There are three USB connectors on thetop of the board. The leftmost one—the one nearest the 9V DCconnector—is for connecting the Altera “Blaster” cable to theworkstation. It is through this connection that the FPGA willbe programmed, that debugging information flows, etc. Theother two USB ports can be used in projects.The DE2 board holds two quartz crystal oscillators (clocksources: little silver boxes labeled with their frequencies). Wewill use the 50 MHz clock for this lab; there is also a 27 MHzclock designed for video timing.The DE2 board has built-in configuration for testing anddemonstration purpose. You can verify the board is workingproperly by observing this default behavior. Use the followingprocedure to power up the DE2 board.First, connect the USB blaster cable from the USB porton the workstation to the USB Blaster connector on the DE2board. Next, connect the 9 V adapter to the DE2’s power con-nector at the top left corner. Third, verify the RUN/PROGswitch on the left edge of the DE2 board (just to the left of theLCD display) is in the RUN position.Power on the DE2 board by pressing the red ON/OFF switchin the upper left corner. The LEDs should flash, the LCDshould display “Welcome to the Altera DE2 Board,” and theVGA output should display an Altera/Terasic logo page.To download our design and override the default configu-ration of the FPGA, we use a JTAG port (JTAG is a ubiquitousstandard that stands for the IEEE Joint Test Action Group).The Altera Quartus tool running on the workstation sends theconfiguration bit stream through the USB cable to the Cy-clone II FPGA. Once programmed, the FPGA retains its con-figuration as long as power is applied to the board; it is lostwhen the power is turned off. We cover the details of this pro-cess below.3 Getting Started with QuartusQuartus is Altera’s development environment for FPGAs. Itconsists of an IDE and a “compiler” that can translate circuitsdescribed in VHDL into configuration data for the FPGA. Startthe Quartus IDE by running thequartuscommand. This re-quires the PATH and LM_LICENSE_FILE environment vari-ables to be set.Altera provides a variety of reference designs for the DE2.For lab 1, we modified the DE2_Top design, which containsinformation about what each pin on the FPGA is connected toand a top-level VHDL module with a port for each pin.Download the lab1.tar.gz file from the class website and ex-tract it with “tar zxf lab1.tar.gz” This will place the project files,listed in Table 1, in the current directory.DE2_TOP.qpf is the top Quartus project file. To open theproject file, use File→Open Project and select DE2_TOP. Oncethe project is opened, you can see and change I/O pin assign-ments with Assignment→Pins. Figure 2 shows this dialog.Table 1: Files in the DE2_TOP projectName RoleDE2_TOP.qpf Quartus Project FileDE2_TOP.qsf Pin assignments, etc.DE2_TOP.vhd Top-level VHDL file1Figure 1: The Altera DE2 boardFigure 2: Assigning Pins TextuallyFor Quartus to configure an FPGA, it must know which pinson the FPGA perform what roles (i.e., what each is named).This information is board-specific since the pins on the FPGAcan be wired to arbitrary peripherals. The DE2_TOP.qsf filecontains this information for the DE2 board.DE2_TOP.vhd is the top-level VHDL module for the project,which mostly lists the top-level ports, i.e., the VHDL names forthe pins. It also sets the state of the LEDs.Although you do not need to modify I/O pin settings for thislab, you may need to do so in the future. Assignment→PinPlanner, shown in Figure 3, opens a display that shows thephysical location the pins on the FPGA and their assignments.4 Compiling for the FPGAThe supplied project can be compiled and downloaded to theboard, altough it does not do much. First, make sure all thesource files are included in the project. From the Project navi-Figure 3: Assigning Pins Graphicallygator window, click on the Files tab. This will display the VHDLfiles that will be compiled into the FPGA. To add a file, selectProject→Add/Remove Files in Project. This opens the windowin Figure 4.Select VHDL files from the pop up window. If you have writ-ten multiple VHDL files, add each of them. Do not add any testbenches (used for simulation) to the list of device design filessince they cannot be compiled into hardware.Now we are ready to compile. Select Processing→StartCompilation to start the compilation process (Figure 5). Thewindow on the left reports progress.A pop-up appears when compilation completes.
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