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MicroBlaze Processor Reference GuideTable of ContentsAbout This GuideManual ContentsAdditional ResourcesConventionsTypographicalOnline DocumentMicroBlaze ArchitectureSummaryOverviewFeaturesInstructionsRegistersGeneral Purpose RegistersSpecial Purpose RegistersProgram Counter (PC)Machine Status Register (MSR)PipelinePipeline ArchitectureBranchesDelay SlotsLoad/Store ArchitectureInterrupts, Exceptions and BreaksInterruptsEquivalent PseudocodeExceptionsEquivalent PseudocodeBreaksSoftware BreaksHardware BreaksInstruction CacheOverviewCache OrganizationCache OperationSoftwareMSR BitWIC InstructionHW Debug LogicLock BitLMB MemoryData CacheOverviewCache OrganizationCache OperationSoftwareMSR BitWDC InstructionHW Debug LogicLock BitLMB MemoryFast Simplex Link InterfaceFSL Read InstructionsBlocking Data Get InstructionNon-blocking Data Get InstructionBlocking Control Get InstructionNon-blocking Control Get InstructionFSL Write InstructionsBlocking Data Put InstructionNon-blocking Data Put InstructionBlocking Control Put InstructionNon-blocking Data Put InstructionDebug InterfaceDebugging FeaturesMicroBlaze Bus InterfacesSummaryOverviewFeaturesBus ConfigurationsTypical Peripheral PlacementConfiguration 1PurposeTypical ApplicationsCharacteristicsConfiguration 2PurposeTypical ApplicationsCharacteristicsConfiguration 3PurposeTypical ApplicationsCharacteristicsConfiguration 4PurposeTypical ApplicationsCharacteristicsConfiguration 5PurposeTypical ApplicationsCharacteristicsConfiguration 6PurposeTypical ApplicationsCharacteristicsFSL ConfigurationAlong with any of the above specified configurations, MicroBlaze can optionally include upto 8 FS...PurposeTypical ApplicationsCharacteresticsBit and Byte LabelingCore I/OBus OrganizationOPB Bus ConfigurationLMB Bus DefinitionAddr[0:31]Byte_Enable[0:3]Data_Write[0:31]ASRead_StrobeWrite_StrobeData_Read[0:31]ReadyClkLMB Bus OperationsGeneric Write OperationGeneric Read OperationBack-to-Back Write Operation (Typical LMB access - 2 clocks per write)Single Cycle Back-to-Back Read Operation (Typical I-side access - 1 clock per read)Back-to-Back Mixed Read/Write Operation (Typical D-side timing)Read and Write Data SteeringFSL Bus OperationMaster FSL signals on MicroBlazeSlave FSL signals on MicroBlazeFSL BUS Timing RequirementsDebug InterfaceImplementationParameterizationMicroBlaze EndiannessDefinitionsBit Naming ConventionsData Types and EndiannessVHDL ExampleBRAM – LMB ExampleInterface Between BRAM and MicroBlazeBRAM Component Declaration (little-endian)Swap BRAM Little-endian Data to Big-endianBRAM InstantiationBRAM – OPB ExampleInterface Between BRAM and MicroBlazeBRAM Component Declaration (little-endian)BRAM InstantiationMicroBlaze Application Binary InterfaceScopeData TypesRegister Usage ConventionsStack ConventionCalling ConventionMemory ModelSmall data areaData areaCommon un-initialized areaLiterals or constantsInterrupt and Exception HandlingMicroBlaze Instruction Set ArchitectureSummaryNotationFormatsType AType BInstructionsaddDescriptionPseudocodeRegisters AlteredLatencyNoteaddiDescriptionPseudocodeRegisters AlteredLatencyNotesandDescriptionPseudocodeRegisters AlteredLatencyandiDescriptionPseudocodeRegisters AlteredLatency1 cycleNoteandnDescriptionPseudocodeRegisters AlteredLatencyandniDescriptionPseudocodeRegisters AlteredLatencyNotebeqDescriptionPseudocodeRegisters AlteredLatencybeqiDescriptionPseudocodeRegisters AlteredLatencyNotebgeDescriptionPseudocodeRegisters AlteredLatencybgeiDescriptionPseudocodeRegisters AlteredLatencyNotebgtDescriptionPseudocodeRegisters AlteredLatencybgtiDescriptionPseudocodeRegisters AlteredLatencyNotebleDescriptionPseudocodeRegisters AlteredLatencybleiDescriptionPseudocodeRegisters AlteredLatencyNotebltDescriptionPseudocodeRegisters AlteredLatencybltiDescriptionPseudocodeRegisters AlteredLatencyNotebneDescriptionPseudocodeRegisters AlteredLatencybneiDescriptionPseudocodeRegisters AlteredLatencyNotebrDescriptionPseudocodeRegisters AlteredLatencyNotebriDescriptionPseudocodeRegisters AlteredLatencyNotesbrkDescriptionPseudocodeRegisters AlteredLatencybrkiDescriptionPseudocodeRegisters AlteredLatencyNotebsDescriptionPseudocodeRegisters AlteredLatencyNotebsiDescriptionPseudocodeRegisters AlteredLatencyNotescmpDescriptionPseudocodeRegisters AlteredLatencyNotesgetDescriptionPseudocodeRegisters AlteredLatencyNotesidivDescriptionPseudocodeRegisters AlteredLatencyNotes.immDescriptionLatencyNotelbuDescriptionPseudocodeRegisters AlteredLatencylbuiDescriptionPseudocodeRegisters AlteredLatencyNotelhuDescriptionPseudocodeRegisters AlteredLatencylhuiDescriptionPseudocodeRegisters AlteredLatencyNotelwDescriptionPseudocodeRegisters AlteredLatencylwiDescriptionPseudocodeRegisters AlteredLatencyNotemfsDescriptionPseudocodeRegisters AlteredLatencyNotemtsDescriptionPseudocodeRegisters AlteredLatencyNotesmulDescriptionPseudocodeRegisters AlteredLatencyNotemuliDescriptionPseudocodeRegisters AlteredLatencyNotesorDescriptionPseudocodeRegisters AlteredLatencyoriDescriptionPseudocodeRegisters AlteredLatencyNoteputDescriptionPseudocodeRegisters AlteredLatencyNotesrsubDescriptionPseudocodeRegisters AlteredLatencyNotesrsubiDescriptionPseudocodeRegisters AlteredLatencyNotesrtbdDescriptionPseudocodeRegisters AlteredLatencyrtidDescriptionPseudocodeRegisters AlteredLatencyrtsdDescriptionPseudocodeRegisters AlteredLatencysbDescriptionPseudocodeRegisters AlteredLatencysbiDescriptionPseudocodeRegisters AlteredLatencyNotesext16DescriptionPseudocodeRegisters AlteredLatencysext8DescriptionPseudocodeRegisters AlteredLatencyshDescriptionPseudocodeRegisters AlteredLatencyshiDescriptionPseudocodeRegisters AlteredLatencyNotesraDescriptionPseudocodeRegisters AlteredLatencysrcDescriptionPseudocodeRegisters AlteredLatencysrlDescriptionPseudocodeRegisters AlteredLatencyswDescriptionPseudocodeRegisters AlteredLatencyswiDescriptionPseudocodeRegister AlteredLatencyNotewdcDescriptionPseudocodeRegisters AlteredLatencyNotewicDescriptionPseudocodeRegisters AlteredLatencyNotexorDescriptionPseudocodeRegisters AlteredLatencyxoriDescriptionPseudocodeRegisters AlteredLatencyNoteRMicroBlazeProcessorReference GuideEmbeddedDevelopment KitEDK (v3.2) April 1, 2003MicroBlaze Processor Reference Guide www.xilinx.com EDK (v3.2) April 1, 20031-800-255-7778EDK (v3.2) April 1, 2003 www.xilinx.com MicroBlaze Processor Reference Guide1-800-255-7778"Xilinx" and the Xilinx logo shown above are registered trademarks of Xilinx, Inc. Any rights not expressly granted herein are
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