CY7C68001Cypress Semiconductor Corporation • 3901 North First Street • San Jose, CA 95134 • 408-943-2600Document #: 38-08013 Rev. *B Revised July 1, 2003CY7C68001EZ-USB SX2™High-Speed USB Interface DeviceCY7C68001 Document #: 38-08013 Rev. *B Page 2 of 50TABLE OF CONTENTS1.0 EZ-USB SX2™ FEATURES .............................................................................................................71.1 Introduction ...............................................................................................................................71.2 Features .....................................................................................................................................71.3 Block Diagram ...........................................................................................................................72.0 APPLICATIONS ...............................................................................................................................82.1 System Diagram ........................................................................................................................83.0 FUNCTIONAL OVERVIEW ..............................................................................................................93.1 USB Signaling Speed ...............................................................................................................93.2 Buses .........................................................................................................................................93.3 Boot Methods ............................................................................................................................93.3.1 EEPROM Organization ....................................................................................................................93.3.2 Default Enumeration .....................................................................................................................103.4 Interrupt System .....................................................................................................................103.4.1 Architecture ...................................................................................................................................103.4.2 ITENABLE Register Bit Definition ...............................................................................................103.5 Resets and Wakeup ................................................................................................................113.5.1 Reset ..............................................................................................................................................113.5.2 USB Reset ......................................................................................................................................113.5.3 Wakeup ..........................................................................................................................................113.6 Endpoint RAM .........................................................................................................................113.6.1 Size .................................................................................................................................................113.6.2 Organization ..................................................................................................................................113.6.3 Endpoint Configurations (High-speed Mode) .............................................................................123.6.4 Default Endpoint Memory Configuration ....................................................................................123.7 External Interface ....................................................................................................................123.7.1 Architecture ...................................................................................................................................123.7.2 Control Signals ..............................................................................................................................133.7.3 IFCLK ..............................................................................................................................................133.7.4 FIFO Access ..................................................................................................................................133.7.5 FIFO Flag Pins Configuration ......................................................................................................143.7.6 Default FIFO Programmable Flag Set-up ....................................................................................143.7.7 FIFO Programmable Flag (PF) Set-up .........................................................................................143.7.8 Command Protocol .......................................................................................................................144.0 ENUMERATION .............................................................................................................................154.1 Standard Enumeration ...........................................................................................................154.2 Default Enumeration ...............................................................................................................165.0 ENDPOINT 0 ..................................................................................................................................166.0 PIN ASSIGNMENTS ......................................................................................................................176.1 56-pin SSOP ............................................................................................................................176.2 56-pin QFN ...............................................................................................................................186.3 CY7C68001 Pin Descriptions .................................................................................................197.0 REGISTER SUMMARY ..................................................................................................................217.1 IFCONFIG Register 0x01 ........................................................................................................227.1.1 Bit 7: IFCLKSRC
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