WEB SERVER FINAL REPORT CSEE4840 Embedded System Design Prof. Steven A. Edwards Franklin Ma Howard Wang Victor Wang William WongTABLE OF CONTENTS 1 OVERVIEW 2 ETHERNET 3 SRAM 4 PROTOCOLS 5 TESTING AND CHALLENGES 6 LESSONS LEARNED 7 CODEOVERVIEW Our aim is to implement a web server on the XESS XSB-300E that will accept requests from clients for data through HTTP over TCP/IP through the onboard Ethernet controller. We will design the VHDL modules that interface with the SRAM, where we will likely store the data that is to be transmitted to the client (unless there is sufficient on-chip memory), and the on-board Ethernet controller. The following protocols will be necessary for our web server: HTTP web page request/response TCP reliable communications IP low-level data transport ICMP * diagnostics (Ping) ARP resolve IP address into MAC address We will be programming these protocols in low-level C to be carried out by MicroBlaze. * ICMP will be used for testing purposes and will be removed to decrease the instruction size if it is possible to fit our code into the BRAM. Block Diagram – General Archtecture:ETHERNET We will be using the AX88796 Ethernet Controller and communicating with it through the custom peripheral on the OPB. The Ethernet Controller interface is outlined below: AX88796 Ethernet ControllerInterfacing with the Controller In general, we will drive the Ethernet Controller by simulating read and write cycles on an ISA bus as follows: • Set the address lines. • During the read cycle, the data lines from the MicroBlaze will serve as inputs. During a write cycle, they will be outputs and be set with the data to be written. • Set the appropriate read or write signals (active low). • If it is a read cycle, the Ethernet controller will drive the bus with the appropriate data. • Deassert the data if it’s a read and latch the data received from the MicroBlaze if it’s a write. • Disable output drivers in order to free up data bus. Timing Diagram for the Ethernet Controller Read Cycle:Write Cycle: Here is the block diagram of the AX88796: AX88796 Block DiagramPackets will be constructed and transmitted according to the Ethernet protocol. We will be initializing and interfacing with the controller through the control registers outlined in the datasheet of the AX88796. Initialization of Ethernet Controller 1) Write 0x21 to the command register to abort current DMA operations 2) Wait 2 ms for it to take effect 3) Write 0x00 to the data control register to enable 8-bit word transfers 4) Write 0x00 to the remote byte count registers to clear remote byte count 5) Write 0x20 to the receive configuration register to set NIC to monitor mode 6) Write 0x02 to the transmission configuration register to set NIC to internal loopback mode 7) Set the Tx start, Rx start, Rx stop and boundary pages by writing the corresponding registers 8) Write 0xff to the interrupt status registers to clear the interrupt flags 9) Write 0x00 to the interrupt mask register to mask all interrupts 10) Write 0x61 to the command register to abort DMA operations 11) Wait 2ms for this to take effect 12) Set the MAC address of the NIC by writing to the physical address registers 13) Set the current Rx page by writing the corresponding register 14) Write 0x20 to the command register to abort DMA operations 15) Write 0x04 to the receive configuration register to set NIC to accept broadcasts 16) Write 0x00 to the transmission configuration register to set normal transfer operations17) Write 0xff to the interrupt status register to clear interrupt flags 18) Write 0x22 to the command register to start the NIC Data Transmission It is necessary to fetch and process incoming packets in small portions. The remote DMA controller is used for this process. Incoming packets will be stored in the SRAM on the controller before attempting to process them. There are two main processes of data transmission: packet reception and packet transmission. Packet Reception During packet reception, we will need to complete the following series of tasks: • Finding the address and length of packet. • Checking for reception of multiple packets. • Checking the packet for error and the packet buffer for overflow. Packet reception is achieved by a local DMA write. The received packets are stored in a buffer ring shown below: The location of the Receive Buffer Ring is set by two registers: Page Start, and Page Stop. Page Start points to the beginning of the buffer ring and Page Stop points to the end of the buffer ring. The DMA address moves through the ring, and whenever it reaches the Page Stop Address, it is reset to the Page Start address. Two registers (Current Page and Boundary Page) is used to initialize the buffer ring and keep the place of all data. The Current Page Register points to the first buffer used to store a packet. It is used to restore DMA for writing status or in case of errors, and acts as a writer pointer. The Boundary Page Register points to the first packet in the buffer that has not yet been read by the host, used to initialize RDMA for removing data, andacts as a read pointer. If the DMA address of the next buffer is equal to the contents of the Page Stop Register and the Boundary Pointer Register, reception of packet is aborted. If the length of the packet is large enough that it uses up the buffer that attempts to store it, the DMA links the next buffer to the current buffer to store the remaining packet. A maximum of 6 buffers will be linked. If the buffer ring Overflow bit indicates overflow, then we proceed to follow the “Resend” procedure as detailed in the Ethernet Controller manual. It is important to note that packet reception needs to be tested to ensure data’s quality. Some testing will involve different packet sizes and high rates of transmission. When receiving a frame the NIC actually adds its own header to the Ethernet header(shown below) indicating the error status, pointer to the next block and length of frame. Packet Transmission During packet transmission, we will need to complete the following series of tasks: • Start the NIC state machine. • Write Ethernet header and packet data into packet buffer. • Set length of the packet, making sure that the length would be rounded up if less than 64 bytes. Local DMA read is used during the
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