Juan Barroso Embedded Systems Design Final Report 5-8-07 Digital Camera Intro: For this design project, the idea was to create a digital camera using the FPGA and a CMOS Sensor. The system itself would require massive time, work, and dedication to implement such an elaborate system. Although the architecture behind this design is fairly simple in nature, the implementation is far from it. When you imagine a digital camera, there are a certain things that come to mind. First, the ability to clearly see the image that you wish to capture a snapshot of plays an important aspect of the design. Clarity in both the image and the display of the photo is what makes for a well rounded camera. Another concept to keep in mind is storage. When looking at a digital camera, there are many different types of external media that can be used to store the image to, such as memory sticks, flash drives, and other forms of memory. The final thing to keep in mind is usability. A digital camera has to be not only easy to use, but also easy to understand its functionality. The user should easily understand how to not only take a photograph, but also how to view the images they have already taken. While others might view the usage of a camera differently, these concepts of the camera are what played a major role in the design of the camera’s architecture. The intended system of the camera was built around these ideas as to how the camera should act, and it was meant to be implemented to the best of abilities on the FPGA.Design and Architecture: The camera, although its architecture seems straight forward and relatively simple, is far more complex than one might imagine. Above is the original diagram of the camera’s architecture. As stated before, this is a complex system. The main reasoning behind this is because the camera itself requires extensive signal processing to produce the image that the user wishes to see. Before diving into the specifics, lets’ take a look at the architecture diagram and go into what it does. The LENS block is the sensor and outputs the data that it is receiving for a given pulse of its clock. One thing to keep in mind is that the FPGA runs with a clock of 50MHz, while the LENS is working with a clock of 25MHz (half the speed). As the data comes out, it is read into the Signal Processor. Within this block alone, a large amount of work is done to the images to begin the process of producing an image to the screen. Within this block, the data is read in and then stripped to the into the color code. This consists of stripping from the data the Red, Green, and Blue values of the image that the lens is capturing.As you can see, as the image comes in and the colors are stripped out, they are coming into the system in a certain order. This order must be maintained so that the image is read properly when being displayed. Also, the pixel order by which the image is being read is also running is the opposite direction that may seem intuitive (the rows are being read in right to left). If the image were displayed to the screen in this manner, it would appear as if you were looking at a mirror image of what you planned to grab a photograph of. After the pixels are read in, and the system begins filtering the RGB values, they are passed to another subsystem whose purpose is to reverse the order of the pixels per row. This would be the equivalent of reading in the pixels left to right. Now that we have the data, the next order of business is one of the concepts behind the camera, storage. We have data, we want to take a picture, but where are we going to put it? With the architecture of this camera, the image will be stored on the FPGA itself, or more so, on the FPGA’s SDRAM. The FPGA has a 512KB SDRAM that we will be using for the storage of the images. From the RAM, it is read into the VGA Controller that will then take the image of the sensor and display it to the screen. Now, although the image passes through the SDRAM initially, it is not stored unless an event is triggered by a button press. The VGA Controller handles the display, taking care ofvertical and horizontal blanking to display the image at a resolution of 640 x 480. After the image is stored on the SDRAM, the user should be able to display the images that were taken on the screen. The subsystems Memory Mangement and Mode Control are the what control this feature. The way it was to be implemented was to allow for a switch event to determine the state of the over all system. If the switch was high, then the images would be read from SDRAM and displayed to the monitor; if the switch was low, the sensor would continue to read images and display them to screen in real time until the image was stored, in which case the image that was captured stayed on the screen until the user instructed the sensor to reset and begin reading data again. This system was created and coded in VHDL, with a master file called Dig_Cam.vhd. Although the main file was in VHDL, as well as other protocols, many of the preexisting files, which were written in Verilog, were used in the creation of this system. The mix of these two types worked fine, it just caused more work to be done to understand the code itself. Next, we discuss the software that worked in the background over the system. Software: In the system that was written, the majority of the work was done in the hardware. This included the connections, signal processing, display, and storage of the images that were taken and to be taken. Software played a major and important role, how the image was stored and displayed afterwards. Typically, given the minimum resolution of a monitor to be 640 x 480 pixels, this means that the total number of pixels to be stored would be 307,200 pixels. With one pixel per byte, the image would require about307KB, leaving only 205 KB of space left, which is insufficient space for the possibility of multiple images on the FPGA itself. So the purpose of the C-coding was to reduce the size of the image before it was stored and then increase the size afterwards. As stated before, the minimum resolution of the monitor is 640 x 480 pixels. To allow for multiple images, we plan to reduce the size of the image by a factor of 4 (half the width and half the length). This would mean that the resolution would then be 320 x 240, which would only be 76,800 pixels or approximately 77 KB. This
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