Using the SDRAM Memory on Altera’s DE2 Boardwith VHDL DesignThis tutorial explains how the SDRAM chip on Altera’s DE2 Development and Education board can be usedwith a Nios II system implemented by using the Altera SOPC Builder. The discussion is based on the assumptionthat the reader has access to a DE2 board and is familiar with the material in the tutorial Introduction to the AlteraSOPC Builder Using VHDL Design.The screen captures in the tutorial were obtained using the QuartusRII version 8.0; if other versions of thesoftware are used, some of the images may be slightly different.Contents:Example Nios II SystemThe SDRAM InterfaceUsing the SOPC Builder to Generate the Nios II SystemIntegration of the Nios II System into the Quartus II ProjectUsing a Phase-Locked Loop1The introductory tutorial Introduction to the Altera SOPC Builder Using VHDL Design explains how thememory in the Cyclone II FPGA chip can be used in the context of a simple Nios II system. For practicalapplications it is necessary to have a much larger memory. The Altera DE2 board contains an SDRAM chipthat can store 8 Mbytes of data. This memory is organized as 1M x 16 bits x 4 banks. The SDRAM chiprequires careful timing control. To provide access to the SDRAM chip, the SOPC Builder implements an SDRAMController circuit. This circuit generates the signals needed to deal with the SDRAM chip.1 Example Nios II SystemAs an illustrative example, we will add the SDRAM to the Nios II system described in the Introduction to theAltera SOPC Builder Using VHDL Design tutorial. Figure 1 gives the block diagram of our example system.On-chipmemoryparallel inputinterfaceparallel outputinterfaceAvalon switch fabricNios II processorJTAG UARTinterfaceUSB-BlasterinterfaceHost computerCyclone IIFPGA chipSW7 SW0 LEDG7 LEDG0Reset_n ClockLEDsJTAG DebugmoduleSwitchesSDRAMcontrollerSDRAMchipFigure 1. Example Nios II system implemented on the DE2 board.The system realizes a trivial task. Eight toggle switches on the DE2 board, SW 7 − 0, are used to turn on or offthe eight green LEDs, LEDG7 − 0. The switches are connected to the Nios II system by means of a parallel I/O2interface configured to act as an input port. The LEDs are driven by the signals from another parallel I/O interfaceconfigured to act as an output port. To achieve the desired operation, the eight-bit pattern corresponding to thestate of the switches has to be sent to the output port to activate the LEDs. This will be done by having the Nios IIprocessor execute an application program. Continuous operation is required, such that as the switches are toggledthe lights change accordingly.The introductory tutorial showed how we can use the SOPC Builder to design the hardware needed to imple-ment this task, assuming that the application program which reads the state of the toggle switches and sets thegreen LEDs accordingly is loaded into a memory block in the FPGA chip. In this tutorial, we will explain how theSDRAM chip on the DE2 board can be included in the system in Figure 1, so that our application program can berun from the SDRAM rather than from the on-chip memory.Doing this tutorial, the reader will learn about:• Using the SOPC Builder to include an SDRAM interface for a Nios II-based system• Timing issues with respect to the SDRAM on the DE2 board• Using a phase-locked loop (PLL) to control the clock timing2 The SDRAM InterfaceThe SDRAM chip on the DE2 board has the capacity of 64 Mbits (8 Mbytes). It is organized as 1M x 16 bits x4 banks. The signals needed to communicate with this chip are shown in Figure 2. All of the signals, except theclock, can be provided by the SDRAM Controller that can be generated by using the SOPC Builder. The clocksignal is provided separately. It has to meet the clock-skew requirements as explained in section 5. Note that somesignals are active low, which is denoted by the suffix N.ClockBank Address 1AddressClock EnableColumn Address StrobeHigh-byte Data MaskCLKCKEADDR[11:0]BA1Bank Address 0Chip SelectRow Address StrobeWrite EnableDataLow-byte Data MaskBA0CS_NCAS_NRAS_NWE_NDQ[15:0]UDQMLDQMSDRAMchipSDRAMcontrollerFigure 2. The SDRAM signals.33 Using the SOPC Builder to Generate the Nios II SystemOur starting point will be the Nios II system discussed in the Introduction to the Altera SOPC Builder Using VHDLDesign tutorial, which we implemented in a project called lights. We specified the system shown in Figure 3.Figure 3. The Nios II system defined in the introductory tutorial.If you saved the lights project, then open this project in the Quartus II software and then open the SOPCBuilder. Otherwise, you need to create and implement the project, as explained in the introductory tutorial, toobtain the system shown in the figure.To add the SDRAM, in the window of Figure 3 select Memories and Memory Controllers > SDRAM >SDRAM Controller and click Add. A window depicted in Figure 4 appears. Select Custom from the Presetsdrop-down list. Set the Data Width parameter to 16 bits and leave the default values for the rest. Since we willnot simulate the system in this tutorial, do not select the option Include a functional memory model in thesystem testbench. Click Finish. Now, in the window of Figure 3, there will be an sdram module added tothe design. Select the command System > Auto-Assign Base Addresses to produce the assignment shown inFigure 5. Observe that the SOPC Builder assigned the base address 0x00800000 to the SDRAM. To make use ofthe SDRAM, we need to configure the reset vector and exception vector of the Nios II processor. Right-click onthe cpu and then select Edit to reach the window in Figure 6. Select sdram to be the memory device for bothreset vector and exception vector, as shown in the figure. Click Finish to return to the System Contents tab andregenerate the system.4Figure 4. Add the SDRAM Controller.Figure 5. The expanded Nios II system.5Figure 6. Define the reset vector and the exception vector.The augmented VHDL entity generated by the SOPC Builder is in the file nios_system.vhd in the directory ofthe project. Figure 7 depicts the portion of the code that defines the port signals for the entity nios_system. Asin our initial system that we developed in the introductory tutorial, the 8-bit vector that is the input to the paral-lel port Switches is called in_port_to_the_Switches. The 8-bit output vector is called out_port_from_the_LEDs.The clock and reset signals are called clk and reset_n, respectively. A
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