This preview shows page 1-2-3-4-5-6-7-8-9-62-63-64-65-66-67-68-69-70-125-126-127-128-129-130-131-132-133 out of 133 pages.
MP3 Player CSEE 4840 SPRING 2010 PROJECT DESIGN Zheng Lai [email protected] Zhao Liu [email protected] Meng Li [email protected] Quan Yuan [email protected] I. Introduction The purpose of the project is to implement a MP3 decoder on DE2 board using Altera FPGA tool chains. Additionally, the decoder extracts the frequency information from the decoded data and uses these data to exhibits a visual effect, “floating histograms”, on the screen, which looks similar to those on classic music player. Our work mainly focuses on building the hardware environment required by this project, implementing the Mpeg 1 Layer III decoding process using low level C programming, and some optimization schemes speeding up the decoding computation within the environment of embedded system. II. Hardware Configuration AB-SAB-MAB-SAB-S Fig.1 System Architecture Fig.1 shows the hardware architecture used in this design. Configuration for each module will be discussed as follows. 2.1 Nios IIDue to high computation demand induced by the Mpeg decoding process, we decided to implement the fastest version of NIOS-II available in SOPC environment, accompanied with a embedded multipliers to speed up the large amount of multiplication in the software. Furthermore, a custom instruction used to compute single precision floating point is also added to the system. 2.2 Audio CODEC WM8731 ADC task is to be performed by audio chip on DE2 board. At the end of decoding process for each frame, 36 16-bit PCM samples for each sub-band are acquired. These digital PCM samples are then put into audio control unit and eventually the audio chip on board produce a analog voltage level according to its digital input. Three modules are needed to translate the decoded result to analog audio output. l WM8731 control unit, serving as an Avalon slave module and providing hardware interface to CPU l A serializer, which handles the parallel-to-serial conversion of the data l First-In-First-Out (FIFO) serving as the buffer structure between the WM8731 control unit and serializer l I2C control unit, used by CPU to configure WM8731 l PPL that generates clock frequency of 11.2896Mhz WM8731 is configured when system is reset. Since the mp3 file we are decoding uses 44.1KHZ sampling rate, to accurately output an analog audio data, we implement a PLL which takes 50Mhz clock a produce 3 clock frequencies: a 50Mhz “back up” clock to CPU, a 11.2896Mhz clock to WM8731, and a clock with 3ns delay with regard to the main clock. The last clock is required by SDRAM for a stable operation. Internal control register need to be set up based on the sampling frequency of the mp3 file we are decoding. The resulting configuration is shown in table. 1 Table .1 Left line in 0x0080 Right Line in 0x0280 Left Head Phone Out 0x047b Right Head Phone Out 0x067b Analog Path Control 0x08d0 Digital Path Control 0x0a04 Power Down Control 0x0c07 Digital Audio Interface Format 0x0e01Sampling Control 0x1020 Active Control 0x1201 Note: The first 9 bits indicates the address of a specific control register. 2.3 VGA A VGA control unit specified in generating the “floating histogram” effect is built in the project. Its functions are described as follows. 2.3.1 Generation of 64 rectangles First, to show 64 rectangles on screen, the horizontal starting points, horizontal ending points and vertical ending points of each rectangle are fixed. The following figure shows the horizontal timing of the VGA: (vertical timing is similar) Fig.2 Define a signal of Hcount. At every rising edge of clk25, Hcount add 1, therefore, Hcount works as a horizontal pointer of the scanning position. When Hcount=HSYNC+HBACK_PORCH+RECTANGLE_HSTART, where RECTANGLE_HSTART represents the horizontal starting point of the rectangle, it means the pointer is moving into the horizontal area of rectangles in the histogram. When Hcount=HSYNC +HBACK_PORCH+RECTANGLE_HEND, where RECTANGLE_HEND represents the horizontal ending point of the rectangle, it means the pointer is moving out of the horizontal area of rectangles in the histogram. During the clock cycle and the clock cycles following, the area on the screen will black out. Having the same function with Hcount, signal Vcount works as a vertical pointer of the scanning position. When Vcount=VSYNC+VBACK_PORCH+RECTANGLE_VSTART, where RECTANGLE_VSTART represents the vertical starting point of the rectangle, it means the pointer is moving into the vertical area of rectangles in the histogram. When Vcount=VSYNC +CBACK_PORCH+RECTANGLE_VEND, where RECTANGLE_VEND represents the vertical ending point of the rectangle, it means the pointer is moving out of the vertical area of rectangles in the histogram. During the clock cycle and the clock cycles following, the area on the screen will black out. The necessary condition for a point on screen to light up is Hcount=HSYNC+HBACK_PORCH+RECTANGLE_HSTART, andVcount=VSYNC+VBACK_PORCH+RECTANGLE_VSTART Which means the pointer is in both the vertical area and horizontal area of rectangles. The 64 rectangles in the histogram are all realized in this way. 2.3.2 Controlling the height of each rectangle with the frequency information from the output of the frequency analyzer. The frequency information is acquired through the decoding software. Specifically, inputs of the function IMDCT (inversed modified discrete cosine transform) are considered to be frequency information for the corresponding PCM samples. We bring these inputs to the VGA controller and adjust the heights, in reality, the vertical starting points for each rectangles based on these inputs. According to the situation that the active area of the screen is 640*480, the ending point of each rectangle in the histogram is chosen to be 380. Therefore, the frequency information input should be from 0 to 380. 2.4 SDRAM Since our decoding process bases on a huge array which represents the bit-stream in the MP3 file, the resulting .elf file would occupy a large amount of memory. As a result, SDRAM, which has larger capacity than SRAM, is necessitated by the design. The Altera DE2 board contains an SDRAM chip that can store 8 Mbytes of data. This memory is organized as 1 M*16 bits*4 banks. The SDRAM chip requires careful timing control. To provide access to the SDRAM chip, the SOPC Builder implements an SDRAM Controller unit. This unit generates the signals needed to deal with SDRAM chip. All of the control signals, except the clock,
View Full Document
Unlocking...