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Columbia CSEE 4840 - Introduction

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Introduction to the Quartus II SoftwarePrefaceDocumentation ConventionsDesign FlowIntroductionGraphical User Interface Design FlowEDA Tool Design FlowDesign Methodologies and PlanningTop-Down and Bottom-Up Design MethodologiesTop-Down Incremental Compilation FlowBottom-Up Incremental Compilation FlowCommand Line And Tcl Design FlowsIntroductionCommand-Line ExecutablesUsing Standard Command-Line Commands & ScriptsUsing Tcl CommandsCreating Makefile ScriptsDesign EntryIntroductionCreating a ProjectUsing RevisionsUsing Version-Compatible DatabasesConverting MAX+PLUS II ProjectsCreating a DesignUsing the Quartus II Block EditorUsing the Quartus II Text EditorUsing the Quartus II Symbol EditorUsing Verilog HDL, VHDL and AHDLUsing the State Machine EditorUsing Altera MegafunctionsUsing Intellectual Property (IP) MegafunctionsUsing the MegaWizard Plug-In ManagerInstantiating Megafunctions in the Quartus II SoftwareInstantiation in Verilog HDL & VHDLUsing the Port & Parameter DefinitionInferring MegafunctionsInstantiating Megafunctions in EDA ToolsUsing the Black Box MethodologyInstantiation by InferenceUsing the Clear Box MethodologyConstraint EntryIntroductionUsing the Assignment EditorUsing the Pin PlannerThe Settings Dialog BoxAssigning Design PartitionsAssigning Design Partitions in the Project NavigatorAssigning Design Partitions with the Design Partitions WindowImporting AssignmentsVerifying Pin AssignmentsSynthesisIntroductionUsing Quartus II Verilog HDL & VHDL Integrated SynthesisUsing Other EDA Synthesis ToolsControlling Analysis & SynthesisUsing Compiler Directives and AttributesUsing Quartus II Logic OptionsUsing Quartus II Synthesis Netlist Optimization OptionsUsing the Design Assistant to Check Design ReliabilityAnalyzing Synthesis Results With the Netlist ViewersThe RTL ViewerThe State Machine ViewerThe Technology Map ViewerPlace and RouteIntroductionPerforming a Full Incremental CompilationAnalyzing Fitting ResultsUsing the Messages Window to View Fitting ResultsUsing the Report Window or Report File to View Fitting ResultsUsing the Chip Planner to Analyze ResultsUsing the Design Assistant to Check Design ReliabilityOptimizing the FitUsing Location AssignmentsSetting Options that Control Place & RouteSetting Fitter OptionsSetting Physical Synthesis Optimization OptionsSetting Individual Logic Options that Affect FittingUsing the Resource Optimization AdvisorUsing the Design Space ExplorerPreserving Assignments through Back-AnnotationBlock-Based DesignIntroductionQuartus II Block-Based Design FlowUsing LogicLock RegionsUsing LogicLock Regions in Top-Down Incremental Compilation FlowsExporting & Importing Partitions for Bottom-Up Design FlowsPreparing the Top-Level Design for a Bottom-Up Incremental Compilation MethodologyExporting a Partition to be Used in a Top-Level ProjectImporting a Lower-Level Partition Into the Top-Level ProjectSimulationIntroductionSimulating Designs with EDA ToolsSpecifying EDA Simulation Tool SettingsGenerating Simulation Output FilesEDA Simulation FlowEDA Tool Functional Simulation FlowNativeLink Simulation FlowManual Timing Simulation FlowSimulation LibrariesSimulating Designs with the Quartus II SimulatorCreating Waveform FilesUsing the Simulator ToolTiming AnalysisIntroductionChoosing the TimeQuest or Classic Timing AnalyzerTimeQuest Timing AnalysisRunning the TimeQuest Timing AnalyzerTasks PaneConsoleReport PaneView PaneClassic Timing AnalysisSpecifying Classic Timing RequirementsSpecifying Project-Wide Classic Timing SettingsSpecifying Individual Timing AssignmentsPerforming a Classic Timing AnalysisPerforming an Early Timing EstimateClassic Timing Analysis ReportingMaking Assignments & Viewing Delay PathsViewing Timing Delays with the Technology Map ViewerPerforming Timing Analysis with EDA ToolsUsing the PrimeTime SoftwareUsing the Tau SoftwareTiming ClosureIntroductionUsing the Chip PlannerChip Planner Tasks And LayersMaking AssignmentsUsing Incremental Compilation to Achieve Timing ClosureUsing the Timing Optimization AdvisorUsing Netlist Optimizations to Achieve Timing ClosureUsing LogicLock Regions to Preserve TimingSoft LogicLock RegionsPath-Based AssignmentsUsing the Design Space Explorer to Achieve Timing ClosurePower AnalysisIntroductionPower Analysis with the PowerPlay Power AnalyzerSpecifying Power Analyzer OptionsUsing the PowerPlay Early Power EstimatorProgramming & ConfigurationIntroductionProgramming One or More Devices With the ProgrammerCreating Secondary Programming FilesCreating Other Programming File FormatsConverting Programming FilesUsing the Quartus II Software to Program Via a Remote JTAG ServerDebuggingIntroductionUsing the SignalTap II Logic AnalyzerSetting Up the SignalTap II Logic AnalyzerUsing the SignalTap II Logic Analyzer with Incremental CompilationAnalyzing SignalTap II DataUsing an External Logic AnalyzerUsing SignalProbeUsing the In-System Memory Content EditorUsing the In-System Sources and Probes EditorUsing the RTL Viewer & Technology Map Viewer For DebuggingUsing the Chip Planner for DebuggingEngineering Change ManagementIntroductionIdentifying Delays & Critical Paths With the Chip PlannerEditing Atoms in the Chip PlannerModifying Resource Properties With the Resource Property EditorViewing & Managing Changes with the Change ManagerVerifying ECO ChangesFormal VerificationIntroductionUsing the Cadence Encounter Conformal SoftwareSpecifying Additional SettingsSystem-Level DesignIntroductionCreating SOPC Designs with SOPC BuilderCreating the SystemGenerating the SystemCreating DSP Designs with the DSP BuilderInstantiating FunctionsGenerating Simulation FilesGenerating Files for SynthesisInstallation, Licensing & Technical SupportInstalling the Quartus II SoftwareLicensing the Quartus II SoftwareGetting Technical SupportDocumentation & Other ResourcesGetting Online HelpStarting the Quartus II Interactive TutorialOther Quartus II Software DocumentationOther Altera LiteratureIndexP25-36149-00MNL-01024-1.0Copyright © 2007 Altera Corporation. All rights reserved. Altera, the stylized Altera logo, specific device designations, and all other words and logos that are identified as trademarks and/or service marks are, unless noted otherwise, the trademarks and service marks of Altera Corpora-tion in the U.S. and other countries. ModelSim is a registered trademark of Mentor Graphics Corporation. All other product or service names are the property of their respective holders. Altera products are protected under


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Columbia CSEE 4840 - Introduction

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