SystemC 1.3Languages for Embedded SystemsProf. Stephen A. EdwardsSummer 2004NCTU, TaiwanDesigning Big Digital SystemsEven Verilog or VHDL’s behavioral modeling is nothigh-level enoughPeople generally use C or C++Standard Methodology for ICsSystem-level designers write a C or C++ modelWritten in a stylized, hardware-like formSometimes refined to be more hardware-likeC/C++ model simulated to verify functionalityModel given to Verilog/VHDL codersVerilog or VHDL specification writtenModels simulated together to test equivalenceVerilog/VHDL model synthesizedDesigning Big Digital SystemsEvery system company was doing this differentlyEvery system company used its own simulation library“Throw the model over the wall” approach makes it easyto introduce errorsProblems:System designers don’t know Verilog or VHDLVerilog or VHDL coders don’t understand system designIdea of SystemCC and C++ are being used as ad-hoc modeling languagesWhy not formalize their use?Why not interpret them as hardware specificationlanguages just as Verilog and VHDL were?SystemC developed at my former employer Synopsys todo just thisWhat Is SystemC?A subset of C++ that models/specifies synchronous digitalhardwareA collection of simulation libraries that can be used to runa SystemC programA compiler that translates the “synthesis subset” ofSystemC into a netlistWhat Is SystemC?Language definition is publicly availableLibraries are freely distributedCompiler is an expensive commercial productSee www.systemc.org for more informationQuick OverviewA SystemC program consists of module definitions plus atop-level function that starts the simulationModules contain processes (C++ methods) and instancesof other modulesPorts on modules define their interfaceRich set of port data types (hardware modeling, etc.)Signals in modules convey information between instancesClocks are special signals that run periodically and cantrigger clocked processesRich set of numeric types (fixed and arbitrary precisionnumbers)ModulesHierarchical entitySimilar to Verilog’s moduleActually a C++ class definitionSimulation involves•Creating objects of this class•They connect themselves together•Processes in these objects (methods) are called bythe scheduler to perform the simulationModulesSC_MODULE(mymod) {/* port definitions *//* signal definitions *//* clock definitions *//* storage and state variables *//* process definitions */SC_CTOR(mymod) {/* Instances of processes and modules */}};PortsDefine the interface to each moduleChannels through which data is communicatedPort consists of a directioninput sc inoutput sc outbidirectional sc inoutand any C++ or SystemC typePortsSC_MODULE(mymod) {sc_in<bool> load, read;sc_inout<int> data;sc_out<bool> full;/* rest of the module */};SignalsConvey information between modules within a moduleDirectionless: module ports define direction of datatransferType may be any C++ or built-in typeSignalsSC_MODULE(mymod) {/* ... *//* signal definitions */sc_signal<sc_uint<32> > s1, s2;sc_signal<bool> reset;/* ... */SC_CTOR(mymod) {/* Instances of modules that connect to the signals */}};Instances of ModulesEach instance is a pointer to an object in the moduleSC_MODULE(mod1) { ... };SC_MODULE(mod2) { ... };SC_MODULE(foo) {mod1* m1;mod2* m2;sc_signal<int> a, b, c;SC_CTOR(foo) {m1 = new mod1("i1"); (*m1)(a, b, c);Connect instance’sports to signalsm2 = new mod2("i2"); (*m2)(c, b);}};ProcessesOnly thing in SystemC that actually does anythingProcedural code with the ability to suspend and resumeMethods of each module classLike Verilog’s initial blocksThree Types of ProcessesMETHOD: Models combinational logicTHREAD: Models testbenchesCTHREAD: Models synchronous FSMsMETHOD ProcessesTriggered in response to changes on inputsCannot store control state between invocationsDesigned to model blocks of combinational logicMETHOD ProcessesSC_MODULE(onemethod) {sc_in<bool> in;sc_out<bool> out;void inverter();Process is simply amethod of this classSC_CTOR(onemethod) {SC_METHOD(inverter);Create an instanceof this processsensitive(in);Trigger when inchanges}};METHOD ProcessesInvoked once every time input “in” changesShould not save state between invocationsRuns to completion: should not contain infinite loopsNot preemptedvoid onemethod::inverter()bool internal;internal = in;Read a value from aportout = internal;Write a value to anoutputTHREAD ProcessesTriggered in response to changes on inputsCan suspend itself and be reactivatedMethod calls wait to relinquish controlScheduler runs it again laterDesigned to model just about anythingTHREAD ProcessesSC_MODULE(onemethod) {sc_in<bool> in;sc_out<bool> out;void toggler();Process a methodof the classSC_CTOR(onemethod) {SC_THREAD(toggler);Create an instanceof the processsensitive << in;Alernate sensitivitylist notation}};THREAD ProcessesReawakened whenever an input changesState saved between invocationsInfinite loops should contain a wait()void onemethod::toggler() {bool last = false;for (;;) {last = in; out = last; wait();Relinquish controluntil the nextchange of signalon this process’ssensitivity listlast = in; out = last; wait();}}CTHREAD ProcessesTriggered in response to a single clock edgeCan suspend itself and be reactivatedMethod calls wait to relinquish controlScheduler runs it again laterDesigned to model clocked digital hardwareCTHREAD ProcessesSC_MODULE(onemethod) {sc_in_clk clock;sc_in<bool> trigger, in;sc_out<bool> out;void toggler();SC_CTOR(onemethod) {SC_CTHREAD(toggler, clock.pos());Instance of thisprocess createdand relevantclock edgeassigned}};CTHREAD ProcessesReawakened at the edge of the clockState saved between invocationsInfinite loops should contain a wait()void onemethod::toggler() {bool last = false;for (;;) {wait_untilRelinquish controluntil the next clockcycle in which thetrigger input is 1(trigger.delayed() == true);last = in; out = last;wait();last = in; out = last;wait();Relinquish control untilthe next clock cycle}}A CTHREAD for Complex Multiplystruct complex_mult : sc_module {sc_in<int> a, b, c, d;sc_out<int> x, y;sc_in_clk clock;void do_mult() {for (;;) {x = a * c - b * d;wait();y = a * d + b * c;wait();}}SC_CTOR(complex_mult) {SC_CTHREAD(do_mult, clock.pos());}};WatchingA CTHREAD process can be given reset-like behaviorSC_MODULE(onemethod) {sc_in_clk clock;sc_in<bool> reset, in;void toggler();SC_CTOR(onemethod) {SC_CTHREAD(toggler, clock.pos());watchingProcess will be restarted from thebeginning when reset is true(reset.delayed() ==
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