Why HDLs?Why HDLs?Why HDLs?Two Separate but Equal LanguagesBasic Lexical Rules of VHDLLiterals in VHDLBitsThe std_logic_1164 packageBoolean OperatorsRules of Boolean Algebra (1)Rules of Boolean Algebra (2)A Full Adder: Truth TableSimplifying Using Boolean RulesStructure of a VHDL ModuleA Full Adder in VHDL...After Logic SynthesisVectors of BitsEndiannessBinary and Hexadecimal in VHDLTwo's ComplementA Hex-to-seven-segment DecoderVHDL: Hex-to-7-segment DecoderFour-to-one mux: when .. elseFour-to-one mux: with...selectThree-to-eight DecoderPriority EncoderInteger ArithmeticA Very Simple ALUArithmetic ComparisonTri-state driversSyntax of ExpressionsSummary of Dataflow ModelingHierarchy: port map positional styleHierarchy: port map by-name styleDirect Instantiation (no component)Generate: Ripple-carry adderProcessesA 4-to-1 mux in the procedural styleA 4-to-1 mux using caseAn Address DecoderSummary of Procedural ModelingBasic D Flip-FlopFlip-Flop with Latch EnableFlip-Flop with Synchronous ResetFour-bit binary counterEight-bit serial in/out shift registerSynchronous RAMA small ROMVariables and SignalsVariables vs. SignalsConstants: A VGA sync generatorRocket Science: FSMsMoore FSMsCoding Moore State MachinesCoding Mealy State MachinesThe Traffic Light ControllerFSM for the Traffic Light ControllerTraffic Light Controller in VHDLTLC in VHDL, continuedTLC in VHDL, concludedThree Modeling Styles: Dataflow (1)Procedural Combinational (2)Three Styles: Procedural Sequential (3)Ten Commandments of VHDLI: Thou Shalt Design Before CodingBlock Diagram of a Character Gen.Pixel-Level TimingStart-of-line DetailEnd-of-line detailII: Thou Shalt be SynchronousIII: Thou Shalt Be SensitiveIII: Thou Shalt Be SensitiveIV: Thou Shalt Assign All Outputs``Default'' values are convenientV: Thou Shalt Enumerate StatesVI:VII: Thou Shalt Avoid AsyncVIII: Thou Shalt Have One VersionIX: Thou Shalt Not Test For X Or ZX: Thou Shalt Not Specify DelaysPitfalls: Boolean vs. Std_logicPitfalls: Inferring a LatchPitfalls: Reading Output PortPitfalls: Complex Port Map ArgsPitfalls: Combinational LoopsPitfalls: Clock GatingPitfalls: Multiple Clock DomainsTestbenchesTestbench MethodologyA TestbenchA testbench continuedDigital Design withSynthesizable VHDLProf. Stephen A. [email protected] UniversitySpring 2009Digital Design with Synthesizable VHDL – p. 1Why HDLs?YBAVddVssBAY1970s: SPICE transistor-level netlistsAn XOR built from four NAND gates.MODEL P PMOS.MODEL N NMOS.SUBCKT NAND A B Y Vdd VssM1 Y A Vdd Vdd PM2 Y B Vdd Vdd PM3 Y A X Vss NM4 X B Vss Vss N.ENDSX1 A B I1 Vdd 0 NANDX2 A I1 I2 Vdd 0 NANDX3 B I1 I3 Vdd 0 NANDX4 I2 I3 Y Vdd 0 NANDDigital Design with Synthesizable VHDL – p. 2Why HDLs?1980s: Graphical schematic capture programsDigital Design with Synthesizable VHDL – p. 3Why HDLs?1990s: HDLs and Logic Synthesislibrary ieee;use ieee.std_logic_1164.all;use ieee.numeric_std.all;entity ALU isport( A: in unsigned(1 downto 0);B: in unsigned(1 downto 0);Sel: in unsigned(1 downto 0);Res: out unsigned(1 downto 0));end ALU;architecture behv of ALU is beginprocess (A,B,Sel) begincase Sel iswhen "00" => Res <= A + B;when "01" => Res <= A + (not B) + 1;when "10" => Res <= A and B;when "11" => Res <= A or B;when others => Res <= "XX";end case;end process;end behv;Digital Design with Synthesizable VHDL – p. 4Two Separate but Equal Languag esVerilog and VHDLVerilog: More succinct, less flexible, really messyVHDL: Verbose, very (too?) flexible, fairl y messyPart of languages people actually use identical.Every synthesis system supports both.Digital Design with Synthesizable VHDL – p. 5Basic Lexical Rules of VHDLFree-form: space only separates tokens.Case-insensitive: “VHDL,” “vHdL,” and “vhdl”are equivalent.Comments: fr om “ --” to the end of the li ne.Identifiers: [a-zA-Z](_?[a-zA-Z0-9])*Examples: X X_or_Y ADDR addrIllegal: 14M CLK__4 FOO_Digital Design with Synthesizable VHDL – p. 6Literals in VHDLDecimal integers∗: 1 42 153_1203Based integers∗: 2#1_0010# 16#F001D#Characters: ’0’ ’1’ ’X’Strings: "101011" "XXXXXX"Bit string literals∗: B"1001_0101" X"95"mean "10010101"∗Underscores added for readability are ignoredDigital Design with Synthesizable VHDL – p. 7Combinational Logic in aDataflow StyleDigital Design with Synthesizable VHDL – p. 8BitsLogical True FalseBinary 1 0Voltag e 1.65–3.3V 0–1.65VTiming DiagramHHH LLLVHDL ’1’ ’0’In VHDL, zeros and ones on wires are membersof an enumerated type.They are not Boolean.Digital Design with Synthesizable VHDL – p. 9The std_logic_1164 packag epackage std_logic_1164 istype std_ulogic is( ’U’,-- Uninitialized’X’, -- Forcing Unknown’0’, -- Forcing 0’1’, -- Forcing 1’Z’, -- High Impedance’W’, -- Weak Unknown’L’, -- Weak 0’H’, -- Weak 1’-’ -- Don’t care);-- The std_logic type allows tri-state drivers (preferred)subtype std_logic is resolved std_ulogic;-- Lots more...Digital Design with Synthesizable VHDL – p. 10Boolean OperatorsThe basic ones in VHDL:a ba and b a or b not a’0’ ’0’ ’0’ ’0’ ’1’’0’ ’1’’0’ ’1’ ’1’’1’ ’0’’0’ ’1’ ’0’’1’ ’1’’1’ ’1’ ’0’a ba nand b a nor b a xor b’0’ ’0’ ’1’ ’1’ ’0’’0’ ’1’’1’ ’0’ ’1’’1’ ’0’’1’ ’0’ ’1’’1’ ’1’’0’ ’0’ ’0’Digital Design with Synthesizable VHDL – p. 11Rules of Boolea n Algebra (1)-- Precedencenot a or b and c = (not a) or (b and c)-- Basic relationshipsnot not a = aa and ’1’ = aa and ’0’ = ’0’a or ’1’ = ’1’a or ’0’ = aa and a = aa and not a = ’0’a or a = aa or not a = ’1’a nand b = not (a and b)a nor b = not (a or b)a xor ’0’ = aa xor ’1’ = not aa xor b = (not a and b) or (a and not b)Digital Design with Synthesizable VHDL – p. 12Rules of Boolea n Algebra (2)-- Commutativitya and b = b and aa or b = b or a-- Associativitya and (b and c) = (a and b) and ca or (b or c) = (a or b) or c-- Distributivitya and (b or c) = a and b or a and ca or (b and c) = (a or b) and (a or c)-- De Morgan’s Lawnot (a and b) = not a or not bnot (a or b) = not a and not bDigital Design with Synthesizable VHDL – p. 13A Full Adder: Truth Tablea b c carry sum0 0 0 0 00 0 10 10 1 0 0 10 1 11 01 0 00 11 0 1 1 01 1 01 01 1 1 1 1carry <=(not a and b and c) or( a and not b and c) or( a and b and not c) or( a and b and c);sum <=(not a and not b and c) or(not a
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