M.A.S.H. Design DocumentWilliam Dang, Chia-Hung Lee, Stephen Lee, Oleg Mironov, and Zijian ZhouApril 3, 20041 IntroductionFor our Embedded Systems Final Design Project, we are implementing a basic karaoke machine. Audio filesin the form of WAVs will be played from the CompactFlash while simultaneously displaying the lyrics of thesong on the screen.2 Design ApproachOur initial step is to first implement the CompactFlash which will store the audio and lyrics. Once we canread specific blocks off the CompactFlash, we need to be able to understand the FAT16 file system to readthe audio and lyrics files properly. Next, we intend to implement the SDRAM memory system to provide away to buffer data from the CF to the SDRAM. Timing will be especially critical. With these componentsin place, we will then interface with the audio codec. We now need to properly share the extracted audiodata between the CompactFlash, the memory buffer, and ultimately the audio codec. Once the basic partswork, we can implement the actual synchronized audio and display of lyrics.3 CompactFlash Interface3.1 IntroductionThe CompactFlash technology is an open standard. It provides a high capacity data storage and I/Ofunctionality. Since our goal is to build a karaoke machine, we will need some space to store all the songsand the text for song lyrics. The C ompactFlash standard provides us a relatively inexpensive and simpleway to accomplish our goal.3.2 Access ModesThe CompactFlash standard provides three access modes: Memory Mode, I/O Mode, and True IDE Mode.The True IDE mode works exactly like the standard IDE interface. I/O mode is often used for non-storagetype devices such as GPS and digital cameras. The Memory Mode method treats the CompactFlash card asa single memory buffer. Since our karaoke machine will necessitate the implementation of many individualcomponents, it will also depend heavily on RAM. The Mem ory Mode of the CompactFlash works similar toRAM access. Thus, we plan to use the Memory Mode in order to shorten the development time .1Figure 1: Overall Implementation of CompactFlash3.3 Design of CompactFlashThe main part of the CompactFlash is the Control Logic. We plan on using VHDL. First, we have tounderstand the timing diagram in the following section and follow the diagram to control the CompactFlashcard. Also, we should build some auxiliary components. One of them, the Card Information StructureROM, will provide the CompactFlash Control Logic with information about the CompactFlash card. Forexample, the CompactFlash Control Logic may require data from the CompactFlash card; it will use theCard Information Structure ROM to retrieve the real meaning of the data. We will also need an AttributeMemory which will store information about the CompactFlash card configuration.In order to control the CompactFlash Control Logic, we should monitor the CompactFlash Control Logicusing some memory buffer where the FAT16 file system will reside and communicate with the CompactFlashControl Logic. In summary, the CompactFlash Control Logic will deal with all the operations related toreading, controlling, and storing data in the memory which will be shared by other parts of our design.3.4 CompactFlash Pins in Memory ModeThe following two tables detail the pins of the CompactFlash interface.2Signal Name Dir Pin DescriptionA10 - A0 I 8, 10, 11, 12, 14,15, 16, 17, 18,19, 20These address lines along with the -REG signal are used toselect the following: The I/O port address registers withinthe CompactFlash Storage Card or CF+ Card, the mem-ory mapped port address registers within the Compact-Flash Storage Card or CF+ Card, a byte in the card’s in-formation structure and its configuration control and sta-tus registers.BVD1 I/O 46 This signal is asserted high, as BVD1 is not supported.BVD2 I/O 45 This signal is asserted high, as BVD2 is not supported.-CD1, -CD2 O 26, 25 These Card Detect pins are connected to ground on theCompactFlash Storage Card or CF+ Card. They are usedby the host to determine that the CompactFlash StorageCard or CF+ Card is fully inserted into its socket.-CE1, -CE2 I 7, 32 These input signals are used both to select the card and toindicate to the card whether a byte or a word operation isbeing performed. -CE2 always accesses the odd byte of theword.-CE1 accesses the even byte or the Odd byte of theword depending on A0 and -CE2. A multiplexing schemebased on A0, -CE1, -CE2 allows 8 bit hosts to access alldata on D0-D7-CSEL I 39 This signal is not used for this mode, but should be con-nected by the host to PC Card A25 or grounded by thehost.D15 - D00 I/O 31, 30, 29, 28,27, 49, 48, 47, 6,5, 4, 3, 2, 23, 22,21These lines carry the Data, Commands and Status infor-mation between the host and the controller. D00 is theLSB of the Even Byte of the Word. D08 is the LSB of theOdd Byte of the Word.GND – 1, 50 Ground.-OE I 9 This is an Output Enable strobe generated by the hostinterface. It is used to read data from the CompactFlashStorage Card or CF+ Card in Memory Mode and to readthe CIS and configuration registers3Signal Name Dir Pin DescriptionREADY O 37 This signal is set high when the CompactFlash StorageCard or CF+ Card is ready to accept a new data transferoperation and is held low when the card is busy. At powerup and at Res et, the READY signal is held low (busy)until the Compact Flash Storage Card or CF+ Card hascompleted its power up or reset function. No access of anytype should be made to the CompactFlash Storage Cardor CF+ Card during this time. Note, however, that whena card is powered up and used w ith +RESET continu-ously disconnected or asserted, the reset function of thispin is disabled and consequently the continuous assertionof +RESET will not cause the READY signal to remaincontinuously in the busy state-REG I 44 This signal is used during Memory Cycles to distinguishbetween Common Memory and Register (Attribute) Mem-ory accesses. High for Common Memory, Low for At-tribute Memory.RESET I 41 When the pin is high, this signal Resets the Compact FlashStorage Card or CF+ C ard. The C ompactFlash StorageCard or CF+ Card is Reset only at power up if this pinis left high or open from power-up. The CompactFlashStorage Card or CF+ Card is also Reset when the SoftReset bit in the Card Configuration Option Register isset.VCC – 13, 38 +5 V, +3.3 V power.-VS1, -VS2 O 33, 40 Voltage Sense Signals. -VS1 is grounded so that the Com-pactFlash Storage Card or CF+ Card CIS can be read at3.3 volts and
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