Embedded System Design Video Game -- Crazy Car (Rally X like) C.C. Liu [email protected] Ying-Der Lee [email protected] 08/26/20051. Introduction The project has been design to take everything that we learned by the class and labs for embedded system. We use both software and hardware implementation by C and VHDL on Xilinx FPGA system. Our target is to demonstrate our knowledge and techniques of embedded system on FPGA learned in the class. 2. The Design 2.1 Game Description We created a game called by “Crazy Car”. It is a labyrinth game like a car to find out the correct path in a maze of roads. Your goal is to find the flag hiding in the map. The car moving is controlled by PS/2 keyboard. The game map that we design is large than VGA (648x480) screen. Therefore, we use screen scrolling to display the car moving and game processing. 2.2 Hardware/VHDL/Video Control In our labs in class, we learned to implement an instant video display on CRT screen. So we develop our design on this basis. The block (tile) size is defined by 8x16 pixels, and the components of the game displayed on the screen are constructed of these 4x2 blocks (tile) called “Big-block”. Our tiles are divided into 3 sets including walls, car, and flag. All of them are constructed of 1 Big-block with 32x32 pixels. For video control, we use timing delay to solve char-column and char-raw display non-harmonious issue. Throughout the implementation, vga_timing tracks the time and the address currently displayed on the screen. It is important to keep track of horizontal and vertical lines on the screen in order to synchronize loading and displaying. These component signals are various other components within the VGA. In addition, we add the RGB setting of each tile for color display.2.3 Software/C/Game State The VGA screen has 80x30 blocks, and the game map of our design is 160x60 that is 4 times of VGA size. That is the map is consisted of 40x30 Big-blocks. Therefore, we set the car in the center of screen and use scrolling screen to display the car moving. The game map is defined and saved in SDRAM initially. Whenever receiving UART interrupt from ps/2 keyboard like up, down, left, or right, we shift the map to corresponding position and the car changes its corresponding direction block. If determining the walls or boundary of the map, we will stop the car moving in the same direction. 3. Block diagram User Input from ps/2 keyboard Game State Software/C UART Interrupt Control SDRAM Initial Map Tile ROM Hardware/VHDL VGA Timing Control Graphical output to CRT Monitor VGA Controller4. Block illustration Wall 1 Big-block is consisted of 8 tiles (block) Game map diagram5. Code //opb_s3board_vga.vhd ------------------------------------------------------------------------------- -- -- Text-mode VGA controller for the Digilent Spartan 3 starter board -- -- Uses an OPB interface, e.g., for use with the Microblaze soft core -- -- Stephen A. Edwards -- [email protected] -- Modified by C.C. Liu and Y.D. Lee ------------------------------------------------------------------------------- library ieee; e ieee.std_logic_arith.all; .all; entity opb_s3board_vga is generic ( C_OPB_AWIDTH : integer := 32; C_OPB_DWIDTH : integer := 32; C_BASEADDR : std_logic_vector(31 downto 0) := X"FEFF1000"; C_HIGHADDR : std_logic_vector(31 downto 0) := X"FEFF1FFF"); port ( OPB_Clk : in std_logic; OPB_Rst : in std_logic; -- OPB signals OPB_ABus : in std_logic_vector (31 downto 0); OPB_BE : in std_logic_vector (3 downto 0); OPB_DBus : in std_logic_vector (31 downto 0); OPB_RNW : in std_logic; t : in std_logic; dr : in std_logic; use ieee.std_logic_1164.all; ususe ieee.std_logic_unsigned OPB_selec OPB_seqAd VGA_DBus : out std_logic_vector (31 downto 0);VGA_errAck : out std_logic; VGA_toutSup : out std_logic; std_logic; : out std_logic; gic; ic; VIDOUT_VSYNC : out std_logic); opb_s3board_vga; "; -- Video parameters ; constant HBACK_PORCH : integer := 48; : integer := 640; 33; ; constant VFRONT_PORCH : integer := 10; ck RAM downto 0); VGA_retry : out std_logic; VGA_xferAck : out std_logic; Pixel_Clock_2x : in -- Video signals VIDOUT_CLK : out std_logic; VIDOUT_RED VIDOUT_GREEN : out std_lo VIDOUT_BLUE : out std_log VIDOUT_HSYNC : out std_logic; end architecture Behavioral of opb_s3board_vga is constant BASEADDR : std_logic_vector(31 downto 0) := X"FEFF1000 constant HTOTAL : integer := 800 constant HSYNC : integer := 96; constant HACTIVE constant HFRONT_PORCH : integer := 16; constant VTOTAL : integer := 525; constant VSYNC : integer := 2; constant VBACK_PORCH : integer := constant VACTIVE : integer := 480 -- 512 X 8 dual-ported Xilinx blo component RAMB4_S8_S8 port ( DOA : out std_logic_vector (7ADDRA : in std_logic_vector (8 downto 0); DIA : in std_logic_vector (7 downto 0); ogic; downto 0); downto 0); downto 0); ENB : in std_logic; gic; WEB : in std_logic); signal ABus : std_logic_vector (31 downto 0); ic_vector (31 downto 0); gnal RNW : std_logic; 31 downto 0); Signals for the OPB-mapped RAM -- Address decode d_logic; -- State bits r(2 downto 0); (7 downto 0); nto 0); signal DOUT0, DOUT1, DOUT2, DOUT3 : std_logic_vector(7 downto 0); ogic_vector(7 downto 0); ogic_vector(7 downto 0); clock divided from 50 MHz gic; -- Shift register control ; -- Input to shift register ic_vector(7 downto 0); -- Shift register data CLKA : in std_logic; ENA : in std_l RSTA : in std_logic; WEA : in std_logic; DOB : out std_logic_vector (7 ADDRB : in std_logic_vector (8 CLKB : in std_logic; DIB : in std_logic_vector (7 RSTB : in std_lo end component; -- Signals latched from the OPB signal DBus : std_log si signal select_delayed : std_logic; -- Latched output signals for the OPB signal DBus_out : std_logic_vector ( -- signal ChipSelect : std_logic; signal MemCycle1, MemCycle2 : st signal RamPageAddress : std_logic_vecto signal RamSelect : std_logic_vector signal RST, WE : std_logic_vector (7 dow signal DOUT4, DOUT5, DOUT6, DOUT7 : std_l signal ReadData : std_l -- Signals for the video
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