Embedded System DesignSummer 2005, NCTU Course ProjectThe Electronic chess gameBySheng-Kuo Lu ( 9395503)Chun Huang ( 9395552)Jang-Yuan Kao ( 9395556)2 of 30AbstractWe have designed a chess game that includes move validation, CHECKchecking, pawn promotion, and undo. It also has a logging system whichshows and can saves what to play and moves.3 of 30Table of ContentsSection Title PageNo1. Overview and Design 42. What we intended to do 43. What we actually did 54. Design Components 54.1 Hardware Description 64.2 VGA controller 65.Who did what 76.VHDL Code 77.C Code 198.CONCLUSION 284 of 301. Overview and DesignThe overall design is to create an electronic check game. User can press thebottom on the keyboard in order to control which one should be moved onthe screen, the output signal from the keyboard will be decoded by FPGA,the movement shall displayed on the screen at the same time.The architecture of synthesis FPGA included main controller / colorcontroller / shift register / board RAM / piece ROM … etc.2. What we intended to doWhat we want to do is to implement the chess games should have movevalidation & CHECK checking, pawn promotion, and undo. It also has alogging system which shows and can saves what to play and moves.5 of 303. What we actually didWhat we actually did was the chess games has move validation & CHECKchecking, pawn promotion.4. Design Components6 of 304.1 Hardware DescriptionThe block diagram above shows the components available in the finalproject. Of those available, we used the monitor as the output videoperipheral.4.2 VGA controllerThis peripheral performs important functions. First, it controls the VGA bygenerating the necessary timing signals (horizontal sync, vertical sync, andblanking, which blanks the video output during horizontal and verticalrefresh), and memory addresses for each pixel, and eventually formats.Second, The glue logic in the main module, opb_xsb300.vhd, whichgenerates the signals and the off-chip drivers for these signals are inpad_io.vhd. It arbitrates access to this memory between the video controllerand the processor. In each cycle, the processor, video, or both may wantaccess to the memory. Since the video absolutely needs the memory when itasks for it the memory controller gives priority to the video system.7 of 305. Who did whatSheng-Kuo Lu ( 9395503)Original design, keyboard control improvement, fonts, error debugging,coding of checking rule.Chun Huang ( 9395552)Graphical display, fonts, writing of final project report.Jang-Yuan Kao ( 9395556)Graphical display, displaying design layouts, coding of checking rule.6. VHDL Code----------------------------------------------------------------------------------- Chess Board VGA controller for the Digilent Spartan 3 starter board---- Uses an OPB interface, e.g., for use with the Microblaze soft core---- Sheng-Kuo Lu-- [email protected] Update from the sample Text Mode VGA controller-- Stephen A. Edwards-- [email protected] below link for further information about chess game.-- http://hk.geocities.com/goodchessclub/main.html-------------------------------------------------------------------------------library ieee;use ieee.std _logic_1164.all;us e ieee.std_logic_arith.al l;use ieee.std_logic_unsi gned.all;entity opb_s3board_vga is generic ( C_OPB_AWIDTH : integer := 32; C_OPB_DWIDTH : integer := 32; C_BASEADDR : std_logic_vector(31 downto 0) := X"FEFF1000";8 of 30 C_HIGHADDR : std_logic_vector(31 downto 0) := X"FEFF1FFF"); port ( OPB_Clk : in std_logic; OPB_Rst : in std_logic; -- OPB signals OPB_ABus : in std_logic_vector (31 downto 0); OPB_BE : in std_logic_vector (3 downto 0); OPB_DBus : in std_logic_vector (31 downto 0); OPB_RNW : in std_logic; OPB_select : in std_logic; OPB_seqAddr : in std_logic; VGA_DBus : out std_logic_vector (31 downto 0); VGA_errAck : out std_logic; VGA_retry : out std_logic; VGA_toutSup : out std_logic; VGA_xferAck : out std_logic; Pixel_Clock_2x : in std_logic; -- Video signals VIDOUT_CLK : out std_logic; VIDOUT_RED : out std_logic; VIDOUT_GREEN : out std_logic; VIDOUT_BLUE : out std_logic; VIDOUT_HSYNC : out std_logic; VIDOUT_VSYNC : out std_logic);end opb_s3board_vga;architecture Behavioral of opb_s3board_vga is constant BASEADDR : std_logic_vector(31 downto 0) := X"FEFF1000"; -- Video parameters constant HTOTAL : integer := 800; constant HSYNC : integer := 96; constant HBACK_PORCH : integer := 48; constant HACTIVE : integer := 640; constant HFRONT_PORCH : integer := 16; constant VTOTAL : integer := 525; constant VSYNC : integer := 2; constant VBACK_PORCH : integer := 33; constant VACTIVE : integer := 480; constant VFRONT_PORCH : integer := 10; -- 2048 X 9 dual-ported Xilinx block RAM component RAMB16_S9_S9 port ( DOA : out std_logic_vector (7 downto 0); DOPA0 : out std_logic; ADDRA : in std_logic_vector (10 downto 0); CLKA : in std_logic; DIA : in std_logic_vector (7 downto 0); DIPA0 : in std_logic; ENA : in std_logic; SSRA : in std_logic; WEA : in std_logic; DOB : out std_logic_vector (7 downto 0); DOPB0 : out std_logic; ADDRB : in std_logic_vector (10 downto 0); CLKB : in std_logic; DIB : in std_logic_vector (7 downto 0); DIPB0 : in std_logic; ENB : in std_logic; SSRB : in std_logic;9 of 30 WEB : in std_logic); end component; -- 512 X 36 dual-ported Xilinx block RAM component RAMB16_S36_S36 port ( DOA : out std_logic_vector (31 downto 0); DOPA : out std_logic_vector(3 downto 0); ADDRA : in std_logic_vector (8 downto 0); CLKA : in std_logic; DIA : in std_logic_vector (31 downto 0); DIPA : in std_logic_vector(3 downto 0); ENA : in std_logic; SSRA : in std_logic; WEA : in std_logic; DOB : out std_logic_vector (31 downto 0); DOPB : out std_logic_vector(3 downto 0); ADDRB : in std_logic_vector (8 downto 0); CLKB : in std_logic; DIB : in std_logic_vector (31 downto 0); DIPB : in std_logic_vector(3 downto 0); ENB : in std_logic; SSRB : in std_logic; WEB : in std_logic); end component; -- Signals latched from the OPB signal ABus : std_logic_vector (31 downto 0); signal DBus : std_logic_vector (31 downto 0); signal RNW : std_logic; signal select_delayed : std_logic; -- Latched output signals for the OPB signal DBus_out : std_logic_vector
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