Altera’s Avalon Communication FabricStephen A. EdwardsColumbia UniversitySpring 2012Altera’s Avalon BusSomething like “PCI on a chip”Described in Altera’s Avalon Memory-Mapped InterfaceSpecification document.Protocol defined between peripherals and the “bus”(actually a fairly complicated circuit).Intended System ArchitectureSource: AlteraMasters and SlavesMost bus protocols draw a distinction betweenMasters: Can initiate a transaction, specify an address,etc. E.g., the Nios II processorSlaves: Respond to requests from masters, cangenerate return data. E.g., a video controllerMost peripherals are slaves.Masters speak a more complex protocolBus arbiter decides which master gains controlThe Simplest Slave PeripheralAvalon-MM Interface(Avalon-MM Slave Port)Application-SpecificInterfacewritedata[15..0]writechipselectclkpio_out[15..0]CLK_EN>D QAvalon-MM PeripheralBasically, “latch when I’m selected and written to.”Naming ConventionsUsed by the SOPC Builder’s New Component Wizard tomatch up VHDL entity ports with Avalon bus signals.type_interface_signaltype is is typically avs for Avalon-MM Slaveinterface is the user-selected name of the interface,e.g., s1.signal is chipselect, address, etc.Thus, avs_s1_chipselect is the chip select signal for aslave port called “s1.”Slave SignalsFor a 16-bit connection that spans 32 halfwords,Slave← clk← reset← chipselect⇐ address[4:0]← read← write⇐ byteenable[1:0]⇐ writedata[15:0]readdata[15:0] →irq →AvalonAvalon Slave Signalsclk Master clockreset Reset signal to peripheralchipselect Asserted when bus accesses peripheraladdress[..] Word address (data-width specific)read Asserted during peripheral→bus transferwrite Asserted during bus→peripheral transferwritedata[..] Data from bus to peripheralbyteenable[..] Indicates active bytes in a transferreaddata[..] Data from peripheral to busirq peripheral→processor interrupt requestAll are optional, as are many others for, e.g.,flow-control and burst transfers.Bytes, Bits, and WordsThe Nios II and Avalon bus are little-endian:31 is the most significant bit, 0 is the leastBytes and halfwords are right-justified:msb lsbByte 3 2 1 0Bit 31 24 23 16 15 8 7 0Word 31 0Halfword 15 0Byte 7 0In VHDLentity avalon_slave isport (avs_s1_clk : in std_logic;avs_s1_reset_n : in std_logic;avs_s1_read : in std_logic;avs_s1_write : in std_logic;avs_s1_chipselect : in std_logic;avs_s1_address : in std_logic_vector(4 downto 0);avs_s1_readdata : out std_logic_vector(15 downto 0);avs_s1_writedata : in std_logic_vector(15 downto 0););end avalon_slave;Basic Async. Slave Read TransferClkAddressreadchipselectreaddataBus cycle starts on rising clock edge.Data latched at next rising edge.Such a peripheral must be purely combinational.Slave Read Transfer w/ 1 Wait StateClkAddressreadchipselectreaddataBus cycle starts on rising clock edge.Data latched two cycles later.Approach used for synchronous peripherals.Basic Async. Slave Write TransferClkAddressreadchipselectwritedataBus cycle starts on rising clock edge.Data available by next rising edge.Peripheral may be synchronous, but must be fast.Basic Async. Slave Write w/ 1 Wait StateClkAddressreadchipselectwritedataBus cycle starts on rising clock edge.Peripheral latches data two cycles later.For slower peripherals.The LED Flasher Peripheral32 16-bit word interfaceFirst 16 halfwords are data to be displayed on the LEDS.Halfwords 16–31 all write to a “linger” register thatcontrols cycling rate.Red LEDs cycle through displaying memory contents.Entity and Architecture Declarationlibrary ieee;use ieee.std_logic_1164.all;use ieee.numeric_std.all;entity de2_led_flasher isport (clk : in std_logic;reset_n : in std_logic;read : in std_logic;write : in std_logic;chipselect : in std_logic;address : in unsigned(4 downto 0);readdata : out unsigned(15 downto 0);writedata : in unsigned(15 downto 0);leds : out unsigned(15 downto 0));end de2_led_flasher;architecture rtl of de2_led_flasher istype ram_type is array(15 downto 0) of unsigned(15 downto 0);signal RAM : ram_type;signal ram_address, display_address : unsigned(3 downto 0);signal counter_delay : unsigned(15 downto 0);signal counter : unsigned(31 downto 0);beginram_address <= address(3 downto 0);Architecture (2)process (clk) beginif rising_edge(clk) thenif reset_n = ’0’ thenreaddata <= (others=>’0’); display_address <= (others=>’0’);counter <= (others => ’0’); counter_delay <= (others=>’1’);elseif chipselect = ’1’ thenif address(4) = ’0’ then -- read or write RAMif read = ’1’ thenreaddata <= RAM(to_integer(ram_address));elsif write = ’1’ thenRAM(to_integer(ram_address)) <= writedata;end if;elseif write = ’1’ then -- Change delaycounter_delay <= writedata;end if; end if;else -- No access to us: update displayleds <= RAM(to_integer(display_address));if counter = x"00000000" thencounter <= counter_delay & x"0000";display_address <= display_address + 1;elsecounter <= counter - 1;end if; end if; end if; end if; end process; end
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