VoIP Design Document Sambuddho Chakravarty Ari Klein Ashish Sharma George SiroisIntroduction: As our project is quite large in scope, we have decided to break it up into two distinct pieces which can be worked on independently. While the general idea behind our project is to create a voice over IP phone system, some of the techniques involved in the compression of the audio signal depart from what is generally regarded as the norm in VoIP communications. Therefore, the first module is a system utilizing the onboard ADC and DAC as well as the FPGA to produce companded signals for transmission. This is a departure from the standard µ-law or similar compression used on VoIP transmissions. The second module is more a more straightforward implementation of all the necessary networking subsystems for VoIP (SIP, RTP, UDP, TCP, and IP). The summaries of e two distinct modules are given below. thSummary of Companding Module: In his research with Professor Yannis Tsividis, Ari Klein extended a technique called companding to digital signal processors. The idea was to reduce the dynamic range of the signals at the input to the ADC, output of the DAC, and internal to the DSP, so that these signals are always large, and thus take full advantage of the available bits in these devices. This should increase the signal to quantization noise ratio at low signal levels. All this should be done without otherwise disturbing the output (in other words, in the absence of quantization, the outputs of the companded and non-companded systems should be identical). For this part of the project, we will be implementing this digital companding technique in hardware on the FPGAs for the case study of a simple digital reverberator. The formulas for accomplishing this have already been derived by Ari Klein and Yannis Tsividis. For the purposes of this project, the important result from those formulas is that for the companding DSP to compute its next state (at time-step n+1) and its companded (always large) output, it requires: • ratios of envelopes of NEXT states (time-step n+1) of the prototype DSP • current state of companded DSP • companded (always large) input Block Diagrams: Conceptually, we want: The input is passed to the prototype (non-companded DSP), digital envelope detection is done on its states, ratios of envelopes are computed. The input envelope is then used to modify the input (the input is divided by its envelope), giving the companded (always large) input, which is passed to the upper ADC. The companded input and the ratios of envelopes are used by the companding DSP (DSPC), along with its current state, to give the compandedoutput. This companded output is then converted back to analog, and given back its envelope, to become the output of the system. Even though the conceptual system on the previous page would “theoretically” work, it is impractical for implementation in this project for several reasons. For example, we only have one ADC, and one DAC, and we also don’t ever want to do division on an FPGA, so computing ratios directly is a bad idea. We will effectively SIMULATE the analog components and the ADCs and DACs on the FPGA. In other words, the actual FPGA’s ADC and DAC will give us inputs and outputs that have more bits than we will use in the “digital processor.” The “analog” operations will be done digitally, but with these extra bits of precision. The ADC’s in the diagram will be simulated by storing the “analog” signals in smaller registers. We plan to use 8 bits for the “digital” part, and either 12 or 16 bits for the “analog” part. To avoid division, we will further restrict the envelopes to be integer powers of 2. This means using a lookup table or some combinational logic to “round” the envelopes (always up) to an integer power of 2. To compute ratios, we need only subtract the powers. The benefits of using integers are that multiplication by these ratios (as is done in the companding DSP) may be accomplished by simple shifts, and that very few bits (at most 3 bits) are required to store the envelope information. This leads to another simplification. The envelope of the input will be computed in the analog domain. We will only make ADCs for the companded input and the power of 2 corresponding to the input envelope, so we only need an 8-bit ADC and a 3-bit ADC. To get the original input back (for processing in the non-companded system), we simply shift the companded input back. Here is some more detail for some of the blocks: The original prototype (non-companding) reverberator: Envelope detection will be done on the input and on the 4 other signals shown (state1, state2001, ymid, and y). We might end up changing the amount of the delays. Also, if we find we have been too ambitious, and are very pressed for time, we might drop the second stage (everything to the right of ymid). Also, we might change the .8 gain to .75 to make it easier to implement.The corresponding companding reverberator (DSPC): The above is only the left half. The right half is topologically the same; the number 1000 should be replaced by 2205, and the inputs and outputs are slightly different. The “product” blocks will simply be implemented as shifters, since the ratios are all integer powers of 2. The envelope detection is accomplished by taking the absolute value and connecting the local maxima. Suppose we want the envelope of x(n). We would connect the points where |x(n)|>|x(n-1)| and |x(n)|>|x(n+1)|. If I am not at such a point, I simply hold my envelope detector output constant (using FFs and MUXs). The block diagram is: For the enabled subsystems (increasing and max), if the enable input is positive, the input is passed to the output. Otherwise, the output is held at its previous value. The “MinMax” block ensures that the envelope never goes below the input, and a small positive number thresh is added to ensure that the envelope is never zero.Required Components: At this point it looks like we will need: • ADC, DAC, audio codec • adders (and sutractors) • lots of MUXs to route signals • lots of FFs for holding state, handling timing, and doing envelope detection • lookup table (or combinational logic) for getting the closest power of 2 larger than a signal (this will decide the shift amount for a particular signal, to ensure that the signal always takes full advantage of
View Full Document
Unlocking...