“High Electron Mobility InAs Nanowire Field-Effect Transistors”OutlineInAs Nanowire FabricationAu catalyst-less InAs Nanowire GrowthBack-gated Device FabricationBack-Gate ResultsTop-gated Device FabricationTop-Gate ResultsConclusions““High Electron Mobility InAs Nanowire Field-EffectTransistors””Shadi A. Dayeh, David P. R. Aplin, Xiaotian Zhou, Paul K. L. Yu,Edward T. Yu, and Deli WangSmall 3 (2): 326-332, 2007Presented by Zachery JacobsonApril 9, 2007OutlineOutlineInAs Nanowire FabricationInAs Nanowire FabricationFabrication without Au catalystsFabrication without Au catalystsBack-gated device fabricationBack-gated device fabricationResultsResultsTop-gated device fabricationTop-gated device fabricationResultsResultsConclusionsConclusionsInAs Nanowire FabricationInAs Nanowire FabricationInAs nanowires are fabricated InAs nanowires are fabricated using MOCVD, with AsH3 and using MOCVD, with AsH3 and TMIn precursorsTMIn precursorsTime = 15 minutesTime = 15 minutesTemperature = 350Temperature = 350°°CCV:III ratio = 25V:III ratio = 25Au colloid diameter = 40 nmAu colloid diameter = 40 nmNanowire diameter = 30-75 nmNanowire diameter = 30-75 nmNanowire length = 20-30 umNanowire length = 20-30 umResulting nanowires are single-Resulting nanowires are single-crystal Wurzitecrystal WurziteGrowth axis = [110]Growth axis = [110]SEM20 umTEM50 nmHRTEM5 nmAu catalyst-less InAs Nanowire GrowthAu catalyst-less InAs Nanowire GrowthB. Mandl, et al, Nano Letters 6 (8): 1817-1821, 2006Au forms deep level traps in Si, limiting Au forms deep level traps in Si, limiting the use of nanowires grown with Au the use of nanowires grown with Au catalysts in hybrid Nanowire/bulk Si catalysts in hybrid Nanowire/bulk Si systemssystemsUsing LP-MOCVD, InAs nanowires were Using LP-MOCVD, InAs nanowires were grown on SiOgrown on SiOx x (x(x≈1) ≈1) No tapering or narrowing of the No tapering or narrowing of the nanowires was foundnanowires was foundThe length of the nanowires is a function The length of the nanowires is a function of the growth temperature, and is fairly of the growth temperature, and is fairly shortshortE-beam lithography can also be used to E-beam lithography can also be used to pattern “islands” of pattern “islands” of SiOSiOxx, that define , that define where nanowires will growwhere nanowires will growSi and InP(111)B substrates were used, Si and InP(111)B substrates were used, although best results were found with although best results were found with InP(111)B substratesInP(111)B substratesBack-gated Device FabricationBack-gated Device FabricationInAs nanowires were InAs nanowires were sonicated from a growth sonicated from a growth substrate in ethanol and substrate in ethanol and transferred to a 600 nm transferred to a 600 nm SiOSiO22/n+ Si substrate/n+ Si substrateE-beam lithography was used E-beam lithography was used to pattern 15 nm Ti/85 nm Al to pattern 15 nm Ti/85 nm Al contacts for the source and contacts for the source and draindrainBack-Gate ResultsBack-Gate ResultsuFE=2740 cm2V-1 s-1Transconductance was Transconductance was found to be 2 uSfound to be 2 uSThis is found to be This is found to be comparable to a free comparable to a free electron gas on the electron gas on the nanowires surfacenanowires surfaceDue to surface states on Due to surface states on SiOSiO22 substrate and S/D substrate and S/D gate coupling due to global gate coupling due to global back gateback gateVDS = 0.5 VTop-gated Device FabricationTop-gated Device FabricationSame steps as back-Same steps as back-gated device followedgated device followedGate was defined using Gate was defined using e-beam lithography using e-beam lithography using 100 nm sputtered SiO2 100 nm sputtered SiO2 and 100 nm of Au gate and 100 nm of Au gate electrodeelectrodeSource drain separations Source drain separations varied from 0.5um to varied from 0.5um to 4um4umTop-Gate ResultsTop-Gate ResultsAnalysis was comprehensiveAnalysis was comprehensiveContact resistance was Contact resistance was calculated to be 1-10 kcalculated to be 1-10 kΩΩ, and , and 1 k1 kΩΩ was used to show worst- was used to show worst-case mobilitycase mobility2-D device simulators were 2-D device simulators were used to calculate gate used to calculate gate capacitancecapacitanceConclusionsConclusionsInAs nanowires can be easily fabricated using InAs nanowires can be easily fabricated using MOCVD technology with or without metal MOCVD technology with or without metal catalyst particlescatalyst particlesThis paper presents a detailed procedure for This paper presents a detailed procedure for collecting mobility values while accounting for collecting mobility values while accounting for contact and series resistance, as well as contact and series resistance, as well as parasitic capacitancesparasitic capacitancesInAs nanowires were found to have great InAs nanowires were found to have great potential as n-type NW FETspotential as n-type NW FETsThank you for your time!
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