Slide 1Slide 2Slide 3Slide 4Slide 5Slide 6Slide 7Slide 8Slide 9Slide 10Slide 11Slide 12Slide 13Slide 14Slide 15Slide 16Slide 17Wookhyun Kwon 1 3/09/2009S-RCAT(Sphere-shaped-Recess-Channel-Array-Transistor) Technology for 70nm DRAM feature size and beyondJ.Y.Kim and Kinam Kim, et all (Samsung Electronics)2005 Symposium on VLSI TechnologyWookhyun KwonWookhyun Kwon 2 3/09/2009This is a story about….Egg of ColumbusHow to solve a difficult problem of DRAM technology.It was a great idea like the Egg of Columbus.Wookhyun Kwon 3 3/09/2009DRAM OperationVstorage = Qc / CstorageStorage CapacitorGateBit LineKey of DRAM operation How long the storage node maintain the stored charge? Target >100msecWookhyun Kwon 4 3/09/2009Xj Scaling RuleParameter Scaling FactorChannel Length (Lch) 1/KTox 1/KNsub KXj 1/K Channel length scaling is a necessity for small cell size. But… Short channel Enhance DIBL Thin gate oxide Enhance GIDL High Nsub & Shallow junction depth Increase junction leakage. We could not obtain sufficient data retention time near 100nm tech. How to solve this problems?DIBLGIDLJunction LeakageMotivation: Data Retention Time IssueWookhyun Kwon 5 3/09/2009Suggested Solutions High Tech. High-K material (for Gox and Storage cap.) Increasing Cs Thick gate oxide SOI (Silicon on Insulator) Reduce DIBLIncreasing Fab. Cost!Wookhyun Kwon 6 3/09/2009Simplest way is… Planar RCAT RCAT (Recessed Channel Array Transistor) DRAM (512Mb, ’03) Long effective channel length & Deep junction depth. Improve refresh characteristicsMaking a long channel length in same area.XjWookhyun Kwon 7 3/09/20091st Generation RCATTech 110nm 90nm 80nm 70nmRecess Depth 150nm 170nm 190n, 200nmVth 1.1V 1.1V 1.2V 1.2VRecess Depth RCAT ScalingBut, by increasing recess depth Sharp curvature problem Gox reliability Uniformity Neck part enlargementChemical Dry EtchingWookhyun Kwon 8 3/09/20092nd Generation RCAT= S-RACTS-RCAT (Shere-shaped RCAT) DRAM (2Gb, ’03) Larger effective channel length Larger curvature small vertical field suppress GIDL Small junction depthPoly VoidWookhyun Kwon 9 3/09/2009Process SequenceOxide spacerIsotropic Dry EtchingKey Process Oxide spacer for protecting Si-neck-enlargement Isotropic dry etch (Low power silicon etch) Steam RTP oxidation or Plasma oxidationWookhyun Kwon 10 3/09/2009Electrical Characteristics Good uniformity of Vth (250mV) Improving DIBL (80mV 40mV) Smaller junction leakage Improving data retention timeWookhyun Kwon 11 3/09/2009Source (IRTS 2006)DRAM Cell Size Trend 46nm (Half pitch) 6F2 S-RCATWe are now here!Who?S-RCATWookhyun Kwon 12 3/09/2009Summary In DRAM technology, the data retention was the big problem. Using RCAT structure, we could solve the problem by increasing the effective channel length in same cell size. It don’t need a significant high-technology. The great idea comes from very simple idea.Wookhyun Kwon 13 3/09/2009Thank you.Questions?Wookhyun Kwon 14 3/09/2009ReferenceWookhyun Kwon 15 3/09/2009More Scaling S-RCAT has a good scalability to sub-50nm. Below 40nm, the isolation between balls (C ) will be a limiter. for further scaling below, another breakthrough in technology is needed.Wookhyun Kwon 16 3/09/20094F2 with Vertical TransistorWookhyun Kwon 17 3/09/20096F2 ArchitectureSource (Samsung) 25% cell size reductionThe 6F2 architecture have Diagonal direction of channel Non-planar channel
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