Twin Silicon Nanowire Field Effect Transistor (TSNWFET)Nanowire FETGAA-TSNWFET FabricationPerformanceTransport Property StudySize Dependence StudyConclusionReferencesTwin Silicon Nanowire Field Effect Transistor(TSNWFET)EE235 PresentationBy: Rhesa NathanaelNanowire FETMotivation:Superior gate control (minimize short channel effects).High drive current.Less sensitive to process variations.Improved transport property.Twin Silicon Nanowire FET demonstrated.GAA-TSNWFET FabricationFully CMOS compatible.Highly reproducible top-down approach.9PerformanceNMOSIon=2.64mA/umIoff=3.1nA/umLg=30nmdNW=10nmTox=2nmPMOSIon=1.11mA/umIoff=5.6pA/umNMOSIon=1.44mA/umIoff=2.0nA/umPMOSIon=1.94mA/umIoff=1.0nA/umLg=15nmdNW=8nmTox=3.5nmTransport Property StudyCoulomb Oscillations single electron tunneling (Lg=45nm, T=4.2K)Conduction quantization (Lg=125nm, up to T~60K)VDS=1~5mVLg=45nmT=4.2KGSDSATVI 5.1in ballistic regimeBallistic transportdNW=10.8nmTox=3.5nmSize Dependence StudyOptimum point: dNW=4nmWhy?Volume inversion dominant until dnw=4nm.Surface, phonon and back scattering dominant below dnw=4nm.ConclusionHigh performance p-type and n-type Twin Silicon Nanowire MOSFETs (TSNWFETs) fabricated using conventional CMOS compatible process.Transport property:Single electron tunneling.Conductance quantization. Ballistic transport. Optimum size: dNW=4nmVolume inversionScatteringReferencesSung Dae Suk, et al., “High performance 5nm radius Twin Silicon Nanowire MOSFET (TSNWFET): Fabrication on Bulk Si Wafer, Characteristics, and Reliability,” IEDM 2005, pp. 717-720.Kyoung Hwan Yeo, et al., “Gate-All-Around (GAA) Twin Silicon Nanowire MOSFET (TSNWFET) with 15nm length gate and 4nm radius nanowires,” IEDM 2006.Keun Hwi Cho, et al., “Observation of single electron tunneling and ballistic transport in twin silicon nanowire MOSFETs (TSNWFETs) fabricated by top-down CMOS process,” IEDM 2006.Sung Dae Suk, et al., “Investigation of nanowire size dependancy on TSNWFET,” IEDM 2007, pp.
View Full Document
Unlocking...