Nanoionics based RRAM Universal Memory T FW 2 Frank Rao 2 Thai Tran Weijian Yang Wai Son Wilson Ko FTW 01 14 2019 EE 235 Final Presentation FTW2 2 EE 235 Final Presentation FTW2 3 EE 235 Final Presentation FTW2 4 EE 235 Final Presentation FTW2 5 EE 235 Final Presentation FTW2 6 Nanoionics based RRAM Universal Memory T FW 2 Frank Rao 2 Thai Tran Weijian Yang Wai Son Wilson Ko FTW 01 14 2019 Outline Memory market Incumbents Memristive RRAM Other competitors Our Choice Flash DRAM Silicon based nano crossbar arrays Conclusion EE 235 Final Presentation FTW2 8 Our Need of Memory Data needs non volatile Data buffering needs fasterresistive RAM Nanoionic based storage Universal memory DRAM Dynamic RAM Flash Memory As fast as DRAM As long data life time as Flash EE 235 Final Presentation FTW2 9 Moore s Law of Memory Source Intel Corporation 2007 EE 235 Final Presentation FTW2 10 Constant Return from Memory Market Memory shares benefits from almost all the other hardware innovations Past Future PC Laptop Next generation wireless network Internet DC Cloud computing Wireless Portable Netbook Device Chip level bio diagnostics EE 235 Final Presentation FTW2 11 Volume of Target Memory Market Annual Memory Revenues in B 2006 2007 2008 2009 DRAM 33 8 31 3 25 7 21 7 NOR 8 6 7 7 6 6 5 7 NAND 11 5 14 5 12 5 10 1 Other 4 6 4 4 4 0 3 6 Memory 58 5 57 9 48 8 41 1 2010 26 5 5 6 12 3 3 6 48 0 2011 29 9 5 6 13 8 3 7 53 0 Source SIA November 2008 6 6B market share even we only replace NOR Flash EE 235 Final Presentation FTW2 12 Outline Memory market Incumbents Memristive RRAM Other competitors Our Choice Flash DRAM Silicon based nano crossbar arrays Conclusion EE 235 Final Presentation FTW2 13 Flash RAM Non volatile Random access only reading and writing Only segmental erasure of data slow writing speed Building blocks are floating gate transistors 1 Transistor for 1 bit http en wikipedia org wiki Flash memory EE 235 Final Presentation FTW2 14 Flash RAM Control gate controls current flow through P region http en wikipedia org wiki Flash memory EE 235 Final Presentation FTW2 15 Flash RAM e Control gate controls current flow through P region e http en wikipedia org wiki Flash memory EE 235 Final Presentation FTW2 16 Flash RAM Control gate controls current flow through P region http en wikipedia org wiki Flash memory EE 235 Final Presentation FTW2 17 Flash RAM Control gate controls current flow through P region Negative charge in float gate can disable p channel http en wikipedia org wiki Flash memory EE 235 Final Presentation FTW2 18 Flash RAM Control gate controls current flow through P region Negative charge in float gate can disable p channel http en wikipedia org wiki Flash memory EE 235 Final Presentation FTW2 19 Flash RAM Reading Process V 0 V 0 Neg charges screen http en wikipedia org wiki Flash memory EE 235 Final Presentation FTW2 20 Flash RAM Writing Process V 0 GND Hot Carrier Injection http en wikipedia org wiki Flash memory EE 235 Final Presentation FTW2 21 Flash RAM Writing Process V 0 V 0 Fowler Nordheim Tunneling http en wikipedia org wiki Flash memory NOTE By design erasing is only possible in blocks in Flash devices EE 235 Final Presentation FTW2 22 NOR and NAND Design NOR NAND http en wikipedia org wiki Flash memory NAND design allows higher densities however NOR design provides faster reading NOTE NAND design uses tunneling for both writing and erasing EE 235 Final Presentation FTW2 23 Dynamic RAM DRAM Volatile Fast true random access stored information should be refreshed at least every 64ms Power Consumption 1 Transistor 1 Capacitor for every bit http en wikipedia org wiki Dynamic random access memory EE 235 Final Presentation FTW2 24 Dynamic RAM DRAM Volatile Fast true random access stored information should be refreshed at least every 64ms Power Consumption 1 Transistor 1 Capacitor for every bit EE 235 Final Presentation FTW2 25 Holy Grail Universal Memory which Satifies Moores Law Memristive RRAM devices are promising candidates EE 235 Final Presentation FTW2 26 Outline Memory market Incumbents Memristive RRAM Other competitors Our Choice Flash DRAM Silicon based nano crossbar arrays Conclusion EE 235 Final Presentation FTW2 27 Nanoionics based Resistive Switching Memory Hysteresis Loop Waser and Aono Nanoionics based resistive switching memories Nature Materials 6 833 840 2007 EE 235 Final Presentation FTW2 28 Insulator Resistive Memories Top Electrode 0V V V Metal oxide Positive Voltage Oxygen deficits Insulator migrates to fill the Oxygen deficits entire metal oxide Dopants Resistance drops Conduct current Bottom Electrode EE 235 Final Presentation FTW2 29 Insulator Resistive Memories Top Electrode 0V V V Positive Voltage Negative Voltage Oxygen deficits migrates to fill the entire metal oxide Resistance drops Oxygen deficits migrates to one side Resistance increases Bottom Electrode EE 235 Final Presentation FTW2 30 Solid Electrolyte Memories Electrochemically Active Anode Ion 0V V V Positive Ion conducting Voltage Ions created at anode material Stopped by inert Resistor cathode Ions Ions buildup Conduct current Effective resistor gets smaller Resistance drops Inert Metal Cathode EE 235 Final Presentation FTW2 31 Solid Electrolyte Memories Electrochemically Active Anode Ion 0V V V Positive Voltage Inert Metal Cathode EE 235 Final Presentation Ions created at anode Stopped by inert cathode Ions buildup Effective resistor gets smaller Resistance drops Negative Voltage FTW2 Bridge dissolves Resistance increases 32 Electron ion Dynamics Hard to Model Coupling of electron ion dynamics was difficult to understand No good mathematical model to predict behavior Hindered development for many years Memristor model predicts behavior well EE 235 Final Presentation FTW2 33 Memristor as a Model Top Electrode 0V Integrate to get Memristance V V Bottom Electrode State variable Strukov et al The missing memristor found Nature 453 80 83 2008 EE 235 Final Presentation FTW2 34 Memristor Model Predicts IV Curve Correctly Hysteresis Loop is the signature of RRAM and memristor Strukov et al The missing memristor found Nature 453 80 83 2008 EE 235 Final Presentation FTW2 35 Outline Memory market Incumbents Memristive RRAM Other competitors Our Choice Flash DRAM Silicon based nano crossbar arrays Conclusion EE 235 Final Presentation FTW2 36 Ferroelectric RAM Ferroelectric Domains Do the Trick for FRAMs Advantage Low power low voltage operation Possible CMOS integration Drawback Destructive readout
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