Slide 1Slide 2Slide 3Slide 4Slide 5Slide 6Slide 7Slide 8Slide 9Slide 10Slide 11Slide 12Slide 13Slide 14Dopant profiling and surface analysisof silicon nanowiresusing capacitance-voltage measurementsErik C. Garnett, Yu-Chih Tseng, Devesh R. Khanal, Junqiao Wu, Jeffrey Bokor, and Peidong Yang, Nature Nanotechnology, March 2009Dopant profiling and surface analysisof silicon nanowiresusing capacitance-voltage measurementsErik C. Garnett, Yu-Chih Tseng, Devesh R. Khanal, Junqiao Wu, Jeffrey Bokor, and Peidong Yang, Nature Nanotechnology, March 2009Changhwan ShinDepartment of Electrical Engineering and Computer Sciences University of California, Berkeley, CA 94720April 27, 20092OutlineOutlineSilicon nanowire structure and fabrication»Structure»FabricationDopant profiling and surface analysis»C-V frequency-dependent measurement»Principle behind dopant profiling»Dopant profiling using high-frequency C-V measurement»FEM 3-D C-V simulationSummary3OutlineOutlineSilicon nanowire structure and fabrication»Structure»FabricationDopant profiling and surface analysis»C-V frequency-dependent measurement»Principle behind dopant profiling»Dopant profiling using high-frequency C-V measurement»FEM 3-D C-V simulationSummary4Completed silicon nanowire [SNW]-FETCompleted silicon nanowire [SNW]-FETSDSOI Lg~2.3µmDevice Fabrication»Growing SNW bridges epitaxially across patterend SOI trench, Using gold nanoparticles and vapour-liquid-solid (VLS) mechanism»Hexagonal faceting of SNW ; <111> oriented wiresBut the surfaces appear to be {211}, instead of {110} in theory{211} commonly observed in micrometer-scale <111> oriented whiskers grown using the VLS mechnism.Device structure»Gate dielectricAl2O3 (15nm), ALD»Metal gate: Chromium»Diameter ~75nm5OutlineOutlineSilicon nanowire structure and fabrication»Structure»FabricationDopant profiling and surface analysis»C-V frequency-dependent measurement»Principle behind dopant profiling»Dopant profiling using high-frequency C-V measurement»FEM 3-D C-V simulationSummary6C-V Freq.-dependent MeasurementC-V Freq.-dependent MeasurementInterface state density, Dit, vs. E-Ev»Using high-low method to extract DitBy comparing high/low-freq. cap. , Dit as a function of E is extracted.Due to underestimation of high-low method, lower bound of Dit is obtained.»Decoupling interface state effects from strain/chemical gating/surface roughnessC-V measurement at 77K»Freq. dispersion in the depletion regionSubstantial shift in C-V»Increased Low-Freq. cap.Interface states (Not responding quickly to High-Freq. a.c.Mid-gap4e11 cm-2ev-11e13 cm-2ev-17OutlineOutlineSilicon nanowire structure and fabrication»Structure»FabricationDopant profiling and surface analysis»C-V frequency-dependent measurement»Principle behind dopant profiling»Dopant profiling using high-frequency C-V measurement»FEM 3-D C-V simulationSummaryDopant profile using the high-Freq. C-VDopant profile using the high-Freq. C-V8“Principle” behind profiling»As SNW is depleted, the effective insulator thickness increases and the capacitance drops.»Voltage dependence of the cap. drop is related to the majority carrier density: Rapid (slow) drop – low (high) dopant concentration.9OutlineOutlineSilicon nanowire structure and fabrication»Structure»FabricationDopant profiling and surface analysis»C-V frequency-dependent measurement»Principle behind dopant profiling»Dopant profiling using high-frequency C-V measurement»FEM 3-D C-V simulationSummaryDopant profile using the high-Freq. C-V [2]Dopant profile using the high-Freq. C-V [2]10Radial dopant profile: Na diff/flat»The expected dopant diffusion profile simulated using the experimental doping conditions as inputs (Na-diff.).»Finite-element modeling (FEM) electrostatic simulations to calculate the corresponding majority carrier distribution (p(r) – diffusion).»Carrier concentration extracted from the theoretical C-V curve with the simulated boron profile as an input (p(r) – simulated)Majority carrier profiling agreed well.»Experimental data matches well to simulated data, but start to diverge towards the core.»Divergence is expected according to the C-V dopant profile resolution limitation of twice the Debye screening length (Ld). Here, Ld is 2 and 13nm at the surface and core, respectively.divergencedivergence11OutlineOutlineSilicon nanowire structure and fabrication»Structure»FabricationDopant profiling and surface analysis»C-V frequency-dependent measurement»Principle behind dopant profiling»Dopant profiling using high-frequency C-V measurement»FEM 3-D C-V simulationSummaryCapacitance-Voltage simulationCapacitance-Voltage simulation12FEM 3-D simulations»Ideal C-V curve generated with diffusion/flat profiles»In order to determine the flat band voltage (Vfb) and to validate the dopant profiling and Dit extraction.»Extra capacitance came from direct coupling between the surround gate and the nanowire leads.»Interface states causes minor deviation in slope.20kHzExtra capacitanceSummarySummary13C-V measurement to determine the Dit profile as a function of position in the band-gap. Comparable Dit of SNW to bulk MOSFET is critical for achieving high-performance electronic devices.Radial boron doping profile was measured via C-V curve and matched the expected profile from dopant diffusion simulation.Q & AQ & AThank you for your
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