NanowiresConnie Chang-Hasnain EECS Dept.UC BerkeleyEE C 235/NSE 203Lecture 132Term Paper Team of three people (2 is not desirable; 4 is not acceptable) Based on open literature and not your own work One presentation (25 min + 5 min Q&A) and one write-up per team Focus on one application, e.g. FED, FET, Solar Cells, Biosensing, lasers, thermal electric devices, gas sensors, electronic devices and circuits, microscopy, optical connects Imagine we are your customers, angels, VCs, or DARPA Program managers. Try to sell “your” approach to us. It would be really nice to have a top-down and bottom-up team on the same device Email me your topic and team members by 4/18 Presentation starts on 5/12 and 5/14 (1-3pm) No class 5/5 and 5/7 Term paper due on 5/15 (a template will be posted on the web).3Should Include: Market and figures-of-merit Technology landscape who else is doing what how? Why nano? And what is nano about it? (not just for the looks!) What are expected to change as we reduce scale? Is it simple scaling or new physics? How different are the results? How do we prove the difference? How do we measure it? How do we use it? What parameters matter in the real world? Competitive advantages: performance and cost If you have the knowledge, you may try to answer How much will it cost and how long will it take for the products to be ready for deployment?4Nanowire-based one-dimensional electronics5E-Beam Litho. for VLS Catalyst Position ControlFabrication ProcessAu dots on GaP substrate.(diameter: 30nm, height: 15nm)6NW Site Control & DH Structures7Planarization of NWs Filling the empty space with polymers while leaving NW tips uncovered – NW top contacts can then be put on!8Possible FET Evolution – Wrapping Gate Properly(a) Typical MOSFET: the planar gate affects the conducting channel from one direction.(b) FINFET: the gate surrounds the channel from all but one side.(c) Nanowire FINFET: complete, but nonuniform wrap-around gate.(d) Vertical nanowire FET: the gate has a complete, uniform wrap-around gate. (e) <Demo> Vertical array of nanowires after wrap-gate formation.9Details of a Vertical NW Transistor10A NW Electronic Device(for NW Parameter Extraction, e.g., Resistivity, Mobility...)OhmiccontactsOhmiccontactDevice #1:4-point measurementsDevice #2:FET with several gates11Nanowire electronic and optoelectronic devices 112Summary of Reported NWs Homogeneous NWs13Summary of Reported NWs Axial DH Structures14Summary of Reported NWs Radial (Core-Shell) DH Structures15FETs with p-Channel or n-Channel(a) 20 nm p-Si NW device (channel length of 1 µm; from red to pink, Vg = -5 V to 3 V)(b) 20 nm n-Si NW device (channel length of 2 µm; from yellow to red, Vg = -5 V to 5 V)Insets: current versus gate-voltage (Ids-Vg) curves recorded for NWFETs plotted on linear (blue) and log (red) scales atVds = -1 V and 1 V, respectively.16NW NOR Gate(Left) Logic NOR gate constructed from a one-by-three crossed NW junction array using one SiNW and three GaN NWs (SEM scale bar, 1 µm)(Right) Output voltage versus the four possible logic address level inputs;inset is the Vo-Vi relation, where the solid and dashed red (blue) lines correspond to Vo-Vi1 and Vo-Vi2 when the other input is 0 (1).174 x 4 Decoder(Left) 4 x 4 Si NW Decoder. The four diagonal cross points in the array were chemically modified (green rectangles) to differentiate their responses from to the input gate lines. Scale bar, 1 µm.(Right) Real-time monitoring of the Vg inputs (blue) and signal outputs (red).18Crossed-NW LEDs(Left) a typical n-InP/p-InP crossed NW device, overlaid with corresponding spatially resolved EL image showing the light emission from the cross point.(Right) Schematic and EL of a tricolor nanoLED array,consisting of a common p-type Si NW crossed with n-type GaN, CdS, and CdSe NWs.19NW Photodetectors(d, Left) I-V characteristic of a n-CdS/p-Si crossed NW APD in dark (black line) and under illumination (red line);inset is the optical micrograph of an array consisting of an n-CdS NW (horizontal) crossing two p-Si NWs (vertical). Scale bar, 10 µm.(e, Right) Spatially resolved photocurrent20PL from a Axial DH NW(Top 1-3) TEM elemental mapping of a single GaAs/GaP nanowire heterojunction,showing the spatial distribution of Ga (gray), P (red), and As (blue) at the junction. Scale bar, 20 nm.(Bottom) Schematic and photoluminescence (PL) image of a 21-layer, (GaP/GaAs)10GaP, NW superlattice.The ten bright regions correspond to GaAs (blue, direct bandgap) regions, while the dark segments are from the GaP (red, indirect bandgap) regions.21A FET with Axial-DH-NW Channel(c, Left) Dark-field optical image of a single NiSi/Si NW superlattice heterostructure. Scale bar is 10 µm.Inset shows a TEM image with scale bar 5 nm.(d, Right) Ids-Vds curves of a NiSi/p-Si/NiSi heterojunction NWFET fabricated using a 30 nm diameter p-Si NW;upper inset is a dark-field optical image with scale bar 3 µm. Lower inset is the Ids-Vg obtained with Vds = -3 V.22Modulation Doped Si NWs(a, top) Schematic and low-resolution TEM image of an n+-n-n+ modulation-doped Si NW. Scale bar, 500 nm.(a, bottom) High-resolution TEM images recorded at the twoends of the NW; scale bar is 10 nm.(b) Scanning gate microscopy images (1-4) of n+-(n-n+)N NWs recorded with a tip voltage of -9 V and Vsd = 1 V. The dark regions represent reduced conductance corresponding to lightly doped NW segments. Scale bars, 1 μm.23Address Decoder based on Modulation-Doped NWs(c) Address decoder. Microscale address wires are inputs. Modulation-doped NWs are outputs.(d) Plots of input (blue) and output (red) voltagesfor the two-by-two decoder configured using two modulation-doped Si NWs as outputs (Out1 and Out2) and two Au metal lines deposited over a uniform Si3N4dielectric as inputs (In1 and In2).24Core-Shell NW as FET Channel(a) Schematic of an undoped Ge/Si core-shell NW and the corresponding band diagram showing the formation of a hole gas in the Ge quantum well confined by the epitaxial Si shell.(b) G-Vgrecorded at different temperatures on a 400 nm long top-gated device;the red, blue, green, and black curves correspond to temperatures of 5 K, 10 K, 50 K, and 100 K, respectively. Insets scale bar, 500 nm.25Passivated GaN NWs(a) Scale bar, 50 nm(b) High electron mobility(c) Corresponding FET data26Nanowire Photonics 1272829NW Manipulation Instrument(a) Side-view schematic
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