Spacer Lithography TechnologyOutlineIC Technology AdvancementLithography ChallengesSpacer Lithography ProcessMultiplication of Pattern DensityAdvantagesDisadvantagesSpacer Lithography TechnologyXin SunEE235 PresentationFeb 13, 2008Outline•Introduction•Spacer Lithography Process•DiscussionIC Technology AdvancementProfessor Tsu-Jae King Liu, FLCC Seminar 2006Lithography Challenges•Continued Scaling of Feature Size–Shorter wavelength–Immersion lithography•Image quality–OPC–Irregularity of masksSpacer Lithography ProcessYang-Kyu Choi, Ji Zhu, Jeff Grunes, Jeffrey Bokor, and Gabor. A. Somorjai, “Fabrication of Sub-10-nm Silicon Nanowire Arrays by Size Reduction Lithography,” J. Phys. Chem. B 2003, 3340-3343.Multiplication of Pattern Density2n lines after n iterations of spacer lithography!Advantages•Sub-lithographic feature sizes–CVD film thickness determines feature size•Tighter CD controlY.-K. Choi et al., IEEE Trans. Electron Devices, Vol. 49, p. 436, 2002Lg LgGate formation by spacer lithography uniform LgGate formation by conventionallithography non-uniform LgY.-K. Choi et al., IEDM Technical Digest, pp. 259-262, 2002Disadvantages•Several spacer lithography steps are needed to obtain different gate lengths.•Additional mask is needed. Geometrical regularity is
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