Slide 1Slide 2Slide 3Slide 4Slide 5Slide 6Slide 7Slide 8Mar. 09, 2009 1Fabrication and Characterization of Gate-All-Around Silicon Nanowires on Bulk Siliconby V. Pott et al., IEEE Transactions on NanotechnologyJaeseok (“Jae”) JeonDept. of Electrical Engineering & Computer SciencesUniversity of California at BerkeleyBerkeley, California 94720-1774Monday, Mar. 09, 2009Mar. 09, 2009 2Motivation•Si-nanowire-based gate-all-around (GAA) MOSFETs via top-down approachRectangularcross-sectionTriangularcross-sectionCircularcross-sectionSiliconcoreGateoxideIDSGateChannellength•Typically, Si-nanowires grown using bottom-up processing•Why top-down processing?» CMOS-compatible» Readily-available resources; has been be dominant technology in semiconductor industryMar. 09, 2009 3Top-Down Technique: Process Flow•LPCVD Si3N4 deposition on top of thermal SiO2 •Si-pillar definition•LPCVD Si3N4 deposition•Isotropic etching•Sacrificial oxide growthB-B’A-A’For devices with triangular Si-nanowire gates,Mar. 09, 2009 4Top-Down Technique: Process Flow (Continued)•Si3N4/SiO2 hard-mask stripping•LTO deposition, followed by CMP•Partial LTO etching•Gate oxidation•In-situ doped LPCVD Poly-Si•Poly-Si definition•Implantation and annealing•LTO deposition•Contact opening•Contact metal deposition, definition and FGAA-A’ B-B’Mar. 09, 2009 5Top-Down Technique:Limitations •Scalability of channel (nanowire) length» Physically limited by lithographic resolution » Sacrificial oxide formed after isotropic etching; channel (nanowire) length increased •Scalability of gate oxide thickness» Thinner gate oxide to drive higher on-current» Thickness non-uniformity; crystalline-orientation-dependent oxidation rateLTOSiNWPolySiSiO21m5nmSiO2SiNWPolySi(a)(b)Si-nanowire encapsulated in Poly-SiMar. 09, 2009 6Top-Down Technique:Limitations (Continued)•Corner effect» Thin oxide grown at corners; reliability issue under high electrical fields•Reproducibility» Wef down to 16 nm by additional sacrificial oxide formations» Sacrificial oxide formed after isotropic etching» Size and shape: dependent upon timed-etch and oxidation timeMar. 09, 2009 7Top-Down Technique:Prospects•In contrast to bottom-up approach,» No need to use any catalyst to initiate growth» Process-controlled doping levels and Si crystal orientation» Localized by lithography and etching» Parallel process → higher throughput» CMOS-compatible» Well-defined ohmic contacts connecting nanowires» Higher yieldMar. 09, 2009 8Top-Down Technique:Prospects (Continued)•Bottom-up approach required for emerging technologies, such as nanotubes and organic semiconductors» Higher density» Allows smaller geometries to be defined; self-assembly → no need for litho» More economical in some sense; c.f. waste of materials during etching» Expected to be more prevalent in semiconductor manufacturing•Combination of top-down and bottom-up approacheshttp://www.imec.be/wwwinter/business/nanotechnology.pdfSilane-grown Si- nanowires using Au catalyst (T=500°C and P=0.8Torr, from J. Albuschies et al., Microelectronic Engineering, Vol. 83,
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