Spacer LithographySlide 2Slide 3Slide 4Slide 5Slide 6Slide 7Spacer LithographyEE C235Tim BakhishevSi - SubstratePoly-SiDummySiO2Spacer ProcessPattern [Dummy] GateDeposit Conformal SiO2Isotropic Etch of SiO2[Remove Dummy Gate] Feature SizeAdvantages of Spacer Process• Feature Size Conformal Deposition Good Control of Film Thickness• Double Feature Density• Reduced VariationDrawback: One Line WidthCan be worked around !Y.K. Choi, et al “Spacer Patterning Technology for Nanoscale CMOS”, TED 2002Sacrificial SiGeFinFET Process FlowLPCVD PSGas thin as 10nmRemove SiGe S/D Pad MaskLarge Line Width Mask (optional)After Gate FormationUTBFET Process FlowSacrificial SiGeLPCVD PSGas thin as 10nmSpacer Mask Final SpacerGate Pad and Large L MaskAfter Gate FormationDouble/Quadruple Fin ProcessStandard (Double) FinQuadruple FinR. Rooyackers, et al “Doubling or quadrupling MuGFET fin …”, IEDM 2006 SiGe Pattern Spacer FormationSiGe RemovalActive Layer PatternSecond Spacer S/D MaskActive Layer PatternConclusionWith S/D PadsWith GateAdvantages:• Greatly Scaled Feature Size• Improved CD Uniformity• Possibilities Beyond LithographyDrawbacks:• Process Complexity• Layout Concerns• Highly Selective Etch Processes
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