EE241 EE241 Spring 2002 Advanced Digital Integrated Circuits Lecture 21 Timing UC Berkeley EE241 B Nikolic Overview l Synchronous Systems Timing methodologies Latching elements Clock distribution Clock generation l Asynchronous Systems UC Berkeley EE241 B Nikolic 1 EE241 References Chapter 11 Clocked storage elements by H Partovi l High speed CMOS design styles Bernstein et al Kluwer 1998 l Unger Tan IEEE Trans Comp 10 86 l Harris Horowitz JSSC 11 97 l Stojanovic Oklobd ija JSSC 4 99 l UC Berkeley EE241 B Nikolic Latch versus Flip Flop l Latch stores data when clock is low l D Q D Q Clk Clk Clk Clk D D Q Q UC Berkeley EE241 Flip Flop stores data when clock rises B Nikolic 2 EE241 Latch Parameters Unger and Tan Trans on Comp 10 86 D Q Clk Clk PWm D TSU TH TClk Q Q TD Q Delays can be different for rising and falling data transitions UC Berkeley EE241 B Nikolic Flip Flop Parameters D Q Clk Clk PWm TH D TSU TClk Q Q Delays can be different for rising and falling data transitions UC Berkeley EE241 B Nikolic 3 EE241 Example Clock System Courtesy of IEEE Press New York 2000 UC Berkeley EE241 B Nikolic Clock Nonidealities l Clock skew Spatial variation in temporally equivalent clock edges deterministic random tSK l Clock jitter Temporal variations in consecutive edges of the clock signal modulation random noise Cycle to cycle short term tJS Long term tJL l Variation of the pulse width for level sensitive clocking UC Berkeley EE241 B Nikolic 4 EE241 Clock Skew and Jitter Clk tSK Clk l l tJS Both skew and jitter affect the effective cycle time Only skew affects the race margin UC Berkeley EE241 B Nikolic Clock Skew of registers Earliest occurrence of Clk edge Nominal Tsk 2 Insertion delay Latest occurrence of Clk edge Nominal Tsk 2 Clk delay Max Clk skew Tsk UC Berkeley EE241 B Nikolic 5 EE241 Longest Logic Path in Edge Triggered Systems TSU Tsk TJS Clk TClk Q TLM P Latest point of launching Earliest arrival of next cycle Unger and Tan Trans on Comp 10 86 UC Berkeley EE241 B Nikolic Clock Constraints in Edge Triggered Systems If launching edge is late and receiving edge is early the data will not be too late if P Tsk TJS TSU Tclk QM TLM Minimum cycle time is determined by the maximum delays through the logic P Tclk QM TLM TSU Tsk TJS Double sided definitions of setup and jitter UC Berkeley EE241 B Nikolic 6 EE241 Shortest Path Earliest point of launching Clk TClk Q TLm Clk TH Nominal clock edge Data must not arrive before this time UC Berkeley EE241 B Nikolic Clock Constraints in Edge Triggered Systems If launching edge is early and receiving edge is late Tclk Qm TLm Tsk TH Minimum logic delay TLm Tsk TH Tclk Qm UC Berkeley EE241 B Nikolic 7 EE241 Clock Constraints in Edge Triggered Systems UC Berkeley EE241 B Nikolic Courtesy of IEEE Press New York 2000 Flip Flop Based Timing Skew Flip flop delay Logic delay TSU TClk Q Flip flop 0 1 Logic UC Berkeley EE241 B Nikolic 8 EE241 Flip Flops and Dynamic Logic Logic delay TSU TSU TClk Q TClk Q 0 0 1 1 Logic delay Precharge Evaluate Evaluate Precharge Flip flops are used only with static logic UC Berkeley EE241 B Nikolic Latch timing When data arrives to transparent latch tD Q D Q Latch is a soft barrier Clk tClk Q When data arrives to closed latch Data has to be re launched UC Berkeley EE241 B Nikolic 9 EE241 Single Phase Clock with Latches Unger and Tan Trans on Comp 10 86 Latch Logic In Chapter 11 Tskl Tskl Tskt Tsk Tskl Tskt Tskt Clk PW P UC Berkeley EE241 B Nikolic Preventing Late Arrivals Clk TSU P PW Data must arrive Clk TSU TClk Q TLM TSU Clk PW TSU TD Q UC Berkeley EE241 TLM B Nikolic 10 EE241 Preventing Late Arrivals Tskl Tskt TSU Tclk QM PW P max TLM T D QM Or P Tclk QM TLM TSU Tskl Tskt PW P TD QM TLM UC Berkeley EE241 B Nikolic Preventing Premature Arrivals PW TH Clk TClk Q TLm Two cases reduce to one TLm Tskl Tskt TH PW TClk Qm UC Berkeley EE241 B Nikolic 11 EE241 Single Latch Timing Bounds on logic delay Tskl Tskt TSU Tclk QM PW P max TLM TD QM TLm Tskl Tskt TH PW TClk Qm Latch Either balance logic delays or make PW short Logic UC Berkeley EE241 B Nikolic Latch Based Design L2 latch is transparent when 1 L1 latch is transparent when 0 L1 Latch Logic L2 Latch Logic UC Berkeley EE241 B Nikolic 12 EE241 Latch Based Timing Skew Static logic L1 Latch Logic L2 latch 1 L2 Latch L1 latch Logic Long path 0 Can tolerate skew Short path UC Berkeley EE241 B Nikolic Latch Based Timing UC Berkeley EE241 B Nikolic 13 EE241 Latch Based Timing l Longest path P 2TD QM TLHM TLLM l Short paths TCLLm TSK TH TClk Qm TCLHm TSK TH TClk Qm UC Berkeley EE241 B Nikolic Latches with Dynamic Logic Clock evaluates logic and opens subsequent latch L2 latch Long path 0 L1 latch Static signals driving dynamic logic must be either non inverting or stable before evaluation 1 Short path UC Berkeley EE241 B Nikolic 14 EE241 Latches with Dynamic Logic Clock opens latch and evaluates subsequent logic L2 latch 1 L1 latch Static signals driving dynamic logic must be either non inverting or stable before latch opens 0 Long path Short path UC Berkeley EE241 B Nikolic Latches with Dynamic Logic Phase1 domino evaluates L2 latch Phase2 domino precharges Clock evaluates logic and opens subsequent latch 0 L1 latch Static signals driving dynamic logic must be either non inverting or stable before evaluation 1 Phase1 domino precharges Phase2 domino evaluates UC Berkeley EE241 Short path B Nikolic 15 EE241 Latches with Dynamic Logic Phase1 domino evaluates Phase2 domino precharges Clock opens latch and evaluates subsequent logic 1 Static signals driving dynamic logic must be either L1 latch non inverting or stable before latch opens L2 latch 0 Phase1 domino precharges Phase2 domino evaluates UC Berkeley EE241 B Nikolic Dynamic Logic with Latches Edges become hard Time available to logic is P 2TD Q UC Berkeley EE241 From Harris B Nikolic 16 EE241 Two Phase Clocking with Latches PW1 Clk TOV PW2 Clk TOV is the overlap time between the phases can be positive or negative Duty cycles can be larger or smaller than 50 Very common example is two phase non overlapping clocking UC Berkeley EE241 B Nikolic 50 Duty Cycle C1 and C2 are two ideal phases C2 C1 L1 Latch Logic L2 Latch S1 Cycle boundary latches CBL UC Berkeley EE241 Logic L1 Latch Logic L2 Latch S1 S2 Mid cycle latches MCL B Nikolic 17 EE241 Soft Edge Properties of Latches Slack passing logical partition uses left over time slack from the previous partition l Time borrowing logical partition utilizes a portion of time allotted to