EE2411UC Berkeley EE241 B. NikolicEE241 - Spring 2002Advanced Digital Integrated CircuitsLecture 13Low Power DesignUC Berkeley EE241 B. NikolicAnnouncementsl Homework #2 due 3/12l Midterm reports due 3/15» ~5 page report, consisting of literature review and detailed outline of future work.EE2412UC Berkeley EE241 B. NikolicGlitching in Static CMOSABXCZABC 101 000XZ Unit Delayalso called: dynamic hazardsObserve: No glitching in dynamic circuitsUC Berkeley EE241 B. NikolicExample 1: Chain of NOR Gates0 1 2 3t (nsec)0.02.04.06.0V (Volt)out1out3out5out7out2out4out6out81out1 out2 out3 out4 out5...EE2413UC Berkeley EE241 B. NikolicExample 2: Adder Circuit0 5 100.02.04.0Time, nsSum Output Voltage, VoltsCinS15S1065432S1Add0 Add1 Add2 Add14 Add15S0 S1 S2 S14 S15CinUC Berkeley EE241 B. NikolicF1F2F3F1F3F2000012000011Equalize Lengths of Timing Paths Through DesignHow to Cope with Glitching?EE2414UC Berkeley EE241 B. NikolicExample: Carry Ripple versus Carry LookaheadA7FA6A5A4A3A2A1A0A0A1A2A3A4A5A6A7FRippleLookaheadUC Berkeley EE241 B. NikolicShort Circuit CurrentsVin VoutCLVddIVDD(mA)0.150.100.05Vin(V)5.04.03.02.01.00.0EE2415UC Berkeley EE241 B. NikolicShort Circuit Currents - UnloadedUC Berkeley EE241 B. NikolicImpact of rise/fall times on short-circuit currentsVDDVoutCLVinISC ≈ 0VDDVoutCLVinISC ≈ IMAXLarge capacitive load Small capacitive loadEE2416UC Berkeley EE241 B. NikolicHow to keep Short-Circuit Currents Low?UC Berkeley EE241 B. NikolicStatic Power ConsumptionVin=5VVoutCLVddIstatPstat= P(In=1).Vdd. Istat• Dominates over dynamic consumption• Not a function of switching frequencyEE2417UC Berkeley EE241 B. NikolicLeakageVoutVddSub-ThresholdCurrentDrain JunctionLeakageSub-Threshold Current Dominant FactorUC Berkeley EE241 B. NikolicSub-Threshold in MOSVT=0.6VT=0.2√IDVGSLower Bound on Threshold to Prevent LeakageEE2418UC Berkeley EE241 B. NikolicSubthreshold Leakage ComponentLeakage control is critical for low-voltage operationVDS=1VID+-VGS0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1.010-1210-1110-1010-910-810-710-610-510-410-310-2ID, AVGS, VVT = 0.4 VVT = 0.1VUC Berkeley EE241 B. NikolicProjected LeakageEE2419UC Berkeley EE241 B. NikolicPrinciples of Power Reductionl Reducing switching probability (α)» Architectures» Power simulators/estimators (time consuming)» Glitching power reduction (15-20%)l Reducing load capacitance» Technology scaling» Gate sizing, minimization, interconnect, CAD» Circuit techniques (PTL, …)l Reducing supply voltage» Quadratic impact on power» Impact on delay – how to maintain throughput?l Reducing frequencyfVVCPDDswingL⋅⋅⋅⋅α~DDswingLVVCE⋅⋅⋅α~UC Berkeley EE241 B. NikolicActive Power Reductionl Reducing switching probability (α)» Architectures» Power simulators/estimators (time consuming)» Glitching power reduction (15-20%)l Reducing load capacitance» Technology scaling» Gate sizing, minimization, interconnect, CAD» Circuit techniques (PTL, …)l Reducing supply voltage» Quadratic impact on power» Impact on delay – how to maintain throughput?l Reducing frequencyfVVCPDDswingL⋅⋅⋅⋅α~DDswingLVVCE⋅⋅⋅α~EE24110UC Berkeley EE241 B. NikolicSupply Voltage Scalingl Fixed throughput applications (e.g. signal processing for communications)» Reduce supply» Maintain throughput by paralellism/pipeliningl Variable throughput (microprocessors)» Dynamic voltage scalingl Relevant metricsUC Berkeley EE241 B. NikolicSupply Voltage Scalingl How to maintain throughput under reduced supply?l Introducing more parallelism/pipelining» Area increase – cost up» Cost/power tradeoffl Multiple voltage domains» Separate supply voltages for different blocks» Lower VDD for slower blocks» Cost of DC-DC converters» Mix cells with different VDDs – level converters l Dynamic voltage scaling – with variable throughputl Reducing VTHto improve speed» Leakage issuesEE24111UC Berkeley EE241 B. NikolicPower and DelayKuroda/SakuraiUC Berkeley EE241 B. NikolicPower-Delay vs Energy-Delay ProductKuroda/SakuraiEE24112UC Berkeley EE241 B. NikolicReducing VddP x td = Et = CL * Vdd2E(Vdd=2)= (CL) * (2)2(CL) * (5)2E(Vdd=5)Strong function of voltage (V2 dependence).Relatively independent of logic function and style.E(Vdd=2) ≈ 0.16 E(Vdd =5)0.030.050.070.10.150.200.300.500.701.001.51 2 551 stage ring oscillator 8-bit adderVdd (volts)quadratic dependenceNORMALIZED POWER-DELAY PRODUCT Power Delay Product Improves with lowering VDD.UC Berkeley EE241 B. NikolicLower VddIncreases DelayCL* VddI=TdTd(Vdd=5)Td(Vdd=2)= (2) * (5 - 0.7)2(5) * (2 - 0.7)2≈4I ~ (Vdd- Vt)2Relatively independent of logic function and style.1.001.502.002.503.003.504.004.505.005.506.006.507.007.502.00 4.00 6.00Vdd(volts)NORMALIZED DELAYadder (SPICE)microcoded DSP chipmultiplieradder ring oscillatorclock generator2.0µm technologyEE24113UC Berkeley EE241 B. NikolicPDP for Different Logic FamiliesChandrakasanJSSC 4/92UC Berkeley EE241 B. NikolicLowering the ThresholdVt = 0.2Vt= 0 IDVGS Reduces the Speed Loss, But Increases LeakageVddDelay2VtEE24114UC Berkeley EE241 B. NikolicReducing Effective CapacitanceGlobal bus architectureLocal bus architectureShared Resources incur Switching OverheadUC Berkeley EE241 B. NikolicArchitecture-Driven Voltage ScalingChandrakasanJSSC 4/92SimpleParallelEE24115UC Berkeley EE241 B. NikolicArchitecture-Driven Voltage ScalingPipelinedParallel-pipelinedUC Berkeley EE241 B. NikolicEnergy-Efficiency Metric: Max ThroughputProcess Queuefrom [Burd95](HICSS 95)EE24116UC Berkeley EE241 B. NikolicPower?SecondOperationsOperationEnergyPower ×=Optimize:•Energy to perform the operation (operations per battery life)•Operations per secondUC Berkeley EE241 B. NikolicDelay and Power under Voltage ScalingEE24117UC Berkeley EE241 B. NikolicProcessors for Portable Devices1000100101Performance (MIPS)Processor Energy (Watt*sec)1 100.1• Eliminate performance ↔ energy trade-off.PDAsPocket-PCsNotebookComputersDynamicVoltageScalingBurdISSCC’00UC Berkeley EE241 B. NikolicProcessor Usage ModeltimeSystem IdleDesiredThroughputMaximum Processor SpeedBackground andhigh-latency processesCompute-intensive andlow-latency processes• Maximize Peak Throughput• Minimize Average Energy/operationSystem Optimizations:BurdISSCC’00EE24118UC Berkeley EE241 B. NikolicCommon Design Approaches (Fixed VDD)Compute ASAP:Delivered ThroughputClock Frequency Reduction:ExcessthroughputAlways high throughputEnergy/operation remains unchanged…while throughput scaled down with