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EE2411UC Berkeley EE241 B. NikolicEE241 - Spring 2000Advanced Digital Integrated CircuitsLecture 10Dynamic LogicUC Berkeley EE241 B. NikolicCascading Dynamic GatesMpMeVDDφφMpMeVDDφφInOut1Out2φOut2Out1InVt∆VVTn(a)(b)Only 0→1 Transitions allowed at inputs!EE2412UC Berkeley EE241 B. NikolicCascading Dynamic LogicUC Berkeley EE241 B. NikolicDomino LogicMpMeVDDPDNφIn1In2In3Out1φMpMeVDDPDNφIn4φOut2MrVDDStatic Inverterwith Level RestorerKrambeck et al, JSSC 6/82EE2413UC Berkeley EE241 B. NikolicDomino Logic - Characteristics• Only non-inverting logic• Very fast - Only 1->0 transitions at input of invertermove VM upwards by increasing PMOS• Adding level restorer reduces leakage andcharge redistribution problems• Optimize inverter for fan-outUC Berkeley EE241 B. NikolicDesigning with Domino LogicMpMeVDDPDNφIn1In2In3Out1φMpMeVDDPDNφIn4φOut2MrVDDInputs = 0during prechargeCan be eliminated!EE2414UC Berkeley EE241 B. NikolicDomino Propertiesl Logic evaluation propagates as falling dominoesl Evaluation period determines the logic depthl The nodes must be precharged during the precharge period (can limit the minimum size of PMOS)l Inputs must be stable (or have only one rising transition) during the evaluationl Gates are ratiolessl Restorer is ratioedl All the gates are non-invertingl Only one transition to be optimizedUC Berkeley EE241 B. NikolicDesign ConsiderationsCharge sharingGround bounceCoupling Leakage (Temperature dependent)Static noise immunity (~VTH)Clock powerTestabilityGndGround bounce:In3In1In2In4VDDOutCLKCLKEE2415UC Berkeley EE241 B. NikolicMultiple-Output Domino (MODL)Hwang, Fisher, ISSCC’88F = F1F2Common subexpressionsUC Berkeley EE241 B. NikolicLookahead AdderMultiple Output Domino (MODL)GeneratePropagateEE2416UC Berkeley EE241 B. NikolicLookahead Adder4-bit group generate 4-bit group propagateUC Berkeley EE241 B. NikolicCompound DominoHouston et al,U.S. Pat. 5,015,882May 1991.EE2417UC Berkeley EE241 B. NikolicClock-Delayed DominoUC Berkeley EE241 B. NikolicClock-Delayed DominoφDDVDφPossible implementation of delay blockNo need for inversionExtensively used in IBM’s 1GHz integer processor (ISSCC’98)EE2418UC Berkeley EE241 B. NikolicIBM’s 1GHz ProcessorSilberman et al, ISSCC’98JSSC 11/98UC Berkeley EE241 B. Nikolicnp-CMOSMpMeVDDPDNφIn1In2In3φMeMpVDDPUNφIn4φOut1Out2Only 1→0 transitions allowed at inputs of PUNGoncavles, De Man JSSC 6/83Friedman, Liu, JSSC 4/84EE2419UC Berkeley EE241 B. Nikolicnp-CMOSOne-bit adderUC Berkeley EE241 B. NikolicNORA LogicMpMeVDDPDNIn1In2In3MeMpVDDPUNIn4Out1Out2To otherN-blocksTo other CLKCLKP-blocksCLKCLKEE24110UC Berkeley EE241 B. NikolicNORA LogicUC Berkeley EE241 B. NikolicNORA LogicEE24111UC Berkeley EE241 B. NikolicNORA LogicφφVDDVDDPDNφIn1In2In3φVDDPUNφφOutφφVDDOutVDDPDNφIn1In2In3φVDDIn4In4VDD(a) φ-module(b) φ-moduleCombinational logic LatchUC Berkeley EE241 B. NikolicNORA LogicEE24112UC Berkeley EE241 B. NikolicNORA LogicUC Berkeley EE241 B. NikolicNORA LogicEE24113UC Berkeley EE241 B. NikolicNORA LogicUC Berkeley EE241 B. NikolicNORA LogicEE24114UC Berkeley EE241 B. NikolicZipper LogicLee, Szeto, Circuits and Devices 5/86UC Berkeley EE241 B. NikolicZipper LogicType I:Type II:EE24115UC Berkeley EE241 B. NikolicClock and Data Precharged LogicDominoCDPDYuan, Svensson, Larson, Electronics Letters, 12/93UC Berkeley EE241 B. NikolicClock and Data Precharged LogicLogicchainsEE24116UC Berkeley EE241 B. NikolicMpMeVDDCLKCLKA B M1M2ABMpCLKO = ABO = ABVDDMf1Mf2Differential (Dual Rail) DominoDynamic CVSL (Clock CVSL) - Heller et al, ISSCC’84UC Berkeley EE241 B. NikolicRegenerative Push-PullDynamic LogicPartovi, DraperISSCC’94EE24117UC Berkeley EE241 B. NikolicRPPDLUC Berkeley EE241 B. NikolicRPPDLEE24118UC Berkeley EE241 B. NikolicRegenerative Push-PullDynamic LogicUC Berkeley EE241 B. NikolicSample-Set Differential LogicDifferential Domino (DCVSL)SSDLGrotjohn JSSC 4/86EE24119UC Berkeley EE241 B. NikolicDifferential Current Switch LogicUC Berkeley EE241 B. NikolicDynamic DCVS-PGEE24120UC Berkeley EE241 B. NikolicSense-Amplifying LogicUC Berkeley EE241 B. NikolicSA-F/FFalling edgeRising edgeEE24121UC Berkeley EE241 B. NikolicDynamic Logic with SA-F/FUC Berkeley EE241 B. NikolicExampleEE24122UC Berkeley EE241 B. NikolicGHz Logic with Sense AmplifiersTakahashi, JSSC


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