1EE241 - Spring 2005Advanced Digital Integrated CircuitsLecture 24-25:Test - MemoryEE241 - Spring 2005Advanced Digital Integrated CircuitsTest23Test - ReferencesRabaey, “Digital Integrated Circuits”Chapter 25, Testing of High-Performance Processors by D.K. Bhavsar4Testing is ExpensiveVLSI testers cost $1-5MVolume manufacturing requires large number of testers, maintenanceTester time costs are in ¢/secTest cost contributes 20-30% to total chip cost35Typical Tester6Types of TestingDiagnosisStress, AgeServiceFunctional testSameSystem IntegrationMan. test, transport ShippingManuf. testPhysical defectsManufactureFunctional testDesign flawsPrototype flawsPrototypeDesign ver.Design flawsDesignTest TypeError SourceStep47Test ClassificationDiagnostic testused in chip/board debuggingdefect localization“go/no go” or production testUsed in chip productionParametric testx ∈ [v,i] versus x ∈ [0,1]check parameters such as NM, Vt, tp, T8Chip DebuggingDesign errors or fabrication defects?Micro-probing the die (1-0.1pF)E-beamSingle-die repair (FIB)59Design for TestabilityM state regsN inputsK outputsK outputsN inputsCombinationalLogicModuleCombinationalLogicModule(a) Combinational function(b) Sequential engine2N patterns 2N+M patternsExhaustive test is impossible or unpractical10Problem: Controllability/ObservabilityCombinational Circuits:controllable and observable - relatively easy to determine test patternsSequential Circuits: State!Turn into combinational circuits or use self-testMemory: requires complex patternsUse self-test611Generating and Validating Test-VectorsAutomatic test-pattern generation (ATPG)for given fault, determine excitation vector (called test vector) that will propagate error to primary (observable) output majority of available tools: combinational networks onlysequential ATPG available from academic researchFault simulationdetermines test coverage of proposed test-vector setsimulates correct network in parallel with faulty networksBoth require adequate models of faults in CMOS integrated circuits12Fault Models01sa0sa1(output)(input)Most Popular - “Stuck - at” modelx1x2x3Zαβγα, γ : x1 sa1β : x1 sa0 orx2 sa0γ : Z sa1Covers almost all (other) occurring faults, such asopens and shorts.713Problem with stuck-at model: CMOS open faultx1x2x1x2ZSequential effectNeeds two vectors to ensure detection!Other options: use stuck-open or stuck-short modelsThis requires fault-simulation and analysis at the switch ortransistor level - Very expensive!14Problem with stuck-at model: CMOS short fault‘0’‘0’‘0’‘1’CABDABCDCauses short circuit betweenVdd and GND for A=C=0, B=1Possible approach:Supply Current Measurement (IDDQ)but: not applicable for gigascaleintegration815Generating and Validating Test-VectorsAutomatic test-pattern generation (ATPG)for given fault, determine excitation vector (called test vector) that will propagate error to primary (observable) output majority of available tools: combinational networks onlysequential ATPG available from academic researchFault simulationdetermines test coverage of proposed test-vector setsimulates correct network in parallel with faulty networksBoth require adequate models of faults in CMOS integrated circuits16Test ApproachesAd-hoc testingScan-based TestSelf-TestProblem is getting harder increasing complexity and heterogeneous combination of modules in system-on-a-chip.Advanced packaging and assembly techniques extend problem to the board level917Scan-based TestLogicCombinationalLogicCombinationalRegisterRegisterOutInScanOutScanInAB18Polarity-Hold SRL (Shift-Register Latch)Introduced at IBM and set as company policy (LSSD) System DataSystem ClockScan DataShift A ClockDCSIAL1L2Shift B ClockBQQSOSO1019Scan-Path Flip-FlopSCANININLOADSCAN PHI2 PHI1KEEPOUTSCANOUT20Scan Flip-Flop in AMD K-61121Intel/HP Itanium 2Naffziger, ISSCC’0222Scan-based Test —OperationTestScanInTestLatchIn0Out0Te s tTestLatchIn1Out1TestTe s tLatchIn2Out2TestTestLatchIn3Out3ScanOutTestφ1φ2N cycles1 cycleevaluationscan-inN cyclesscan-out1223Scan Test24Self-test(Sub)-CircuitUnderTestStimulus Generator Response AnalyzerTest ControllerRapidly becoming more important with increasingchip-complexity and larger modules1325Linear-Feedback Shift Register (LFSR)S0S1S2RRR1 0 00 1 01 0 11 1 01 1 10110 0 11 0 0Pseudo-Random Pattern Generator26Signature AnalysisRCounterInCounts transitions on single-bit stream ≡ Compression in time1427BILBOS0RR RS1S2ScanOutScanInmuxD2D1D0B0B1Operation modeB0 NormalScanSignature analysis110010Pattern generation or0 1 ResetB128BILBO ApplicationLogicCombinationalLogicCombinationalBILBO-BBILBO-AOutInScanIn ScanOut1529Built-In Self-Test30Memory Self-TestFSMMemorySignatureAnalysisUnder Testdataaddress &R/W control-indata-outPatterns: Writing/Reading 0s, 1s, Walking 0s, 1sGalloping 0s, 1s1631Boundary Scan (JTAG)Printed-circuit boardLogicscan pathnormal interconnectPackaged ICBonding PadScan-inScan-outsi soBoard testing becomes as problematic as chip testing32Testing on-chip Logic1733Testing Mixed Analog-Digital ICs34Embedded Software-Based Self-Testing for Programmable System ChipsBusInterface Master WrapperBusArbiterLow-CostTesterOn-ChipMemoryTest programResponsesVCISignaturesDSPVCIIP CoreVCISystem MemoryVCIOn-chip BusBusInterfaceMaster WrapperBusInterface Target WrapperBusInterface Target WrapperLoading test program at low speedSelf-test at operational speedUnloading response signature at low speedLow-cost testerHigh-quality at-speed testLow test overheadNon-intrusiveTest in normal operational modeNo violation of power consumptionMore accurate