1EE241 - Spring 2005Advanced Digital Integrated CircuitsLecture 19:Timing –Latch based and asynchronous2Self-timed DesignReadingChapter 9, Self-Timed Pipelines, by T. WilliamsChapter 10 in Rabaey et al23Self-timed and Asynchronous DesignFunctions of clock in synchronous design1) Acts as completion signal2) Ensures the correct ordering of eventsTruly asynchronous design2) Ordering of events is implicit in logic1) Completion is ensured by careful timing analysisSelf-timed design1) Completion ensured by completion signal2) Ordering imposed by handshaking protocol4Synchronous DatapathIntpd,regtpd1DR1QCLKLogicBlock #1tpd2DR2QLogicBlock #2tpd3DR3Q DR4QLogicBlock #335Self-Timed Pipelined DatapathHSReqAckIn OutStart DonetpF1HSReqAckHSReqAckReqAckR1 F1Start DonetpF2R2 F2Start DonetpF3R3 F36Completion Signal GenerationLOGICNETWORKDELAY MODULEInOutStartDoneUsing Delay Element (e.g. in memories)47Completion Signal GenerationUsing Redundant Signal Encoding8Completion Signal in DCVSLPDNStartB0B0B1B1In1StartIn1PDNDoneVDDVDDIn2In259Self-Timed AdderP0C0P1G0P2G1P3G2G3VDDStartStartP0C0P1K0P2K1P3K2K3VDDStartStartC0C1C2C3C4C4C4C0C1C2C3C4VDDStartC4C3C2C1C4C3C2C1StartDone(a) Differential carry generation(b) Completion signal10Hand-Shaking Protocol113RECEIVERSENDERReqReqAckDataAckData(a) Sender-receiver configuration(b) Timing diagramcycle 1 cycle 2Sender’s actionReceiver’s action2Two Phase Handshake611Event Logic – The Muller-C ElementAB Fn+10011010(b) Truth table(a) Schematic10FnFn1FABCSFFRQAB(a) Logic(b) Majority Function(c) DynamicABBBAVDDBFABVDDVDD122-Phase Handshake ProtocolAdvantage : FAST - minimal # of signaling events (important for global interconnect)Disadvantage : edge - sensitive, has stateSenderlogicReceiverlogicDataHandshake logicData ready Data acceptedCReqAck713Example: Self-timed FIFOAll 1s or 0s -> pipeline emptyAlternating 1s and 0s -> pipeline fullCCR1InOutEnAckiReqiR2R3CReq0AckoDone142-Phase Protocol815ExampleFrom [Horowitz]16Example917Example18Example10194-Phase Handshake ProtocolSlower, but unambiguousAlso known as RTZ1 123 54ReqAckDataCycle 1 Cycle 2Sender’s actionReceiver’s action204-Phase Handshake ProtocolImplementation using Muller-C elementsHandshake logicData readyData acceptedReqSAckC CSenderlogicReceiverlogicData1121Self-Resetting LogicPrechargedLogic Block(L1)PrechargedLogic Block(L2)PrechargedLogic Block(L3)completiondetection(L1)completiondetection(L2)completiondetection(L3)VDDAB CintoutPost-chargelogic22Asynchronous-Synchronous InterfaceAsynchronoussystemSynchronous systemSynchronizationfCLKfin1223Synchronizers and ArbitersArbiter: Circuit to decide which of 2 events occurred firstSynchronizer: Arbiter with clock φ as one of the inputsProblem: Circuit HAS to make a decision in limited time - which decision is not importantCaveat: It is impossible to ensure correct operationBut, we can decrease the error probability at the expense of delay24A Simple Synchronizer • Data sampled on rising edge of the clock• Latch will eventually resolve the signal value,but ... this might take infinite time!CLKintI2I1DQCLK1325Synchronizer: Output Trajectories Single-pole model for a flip-flop2.01.00.00 100 200 300Vouttime [ps]26Mean Time to Failure1427ExampleTf = 10 nsec = TTsignal = 50 nsectr = 1 nsect = 310 psecVIH - VIL = 1 V (VDD = 5 V)N(T) = 3.9 10-9 errors/secMTF (T) = 2.6 108 sec = 8.3 yearsMTF (0) = 2.5 µsec28Influence of NoiseInitial Distributionp(v)0VILVIHTUniform distributionaround VM Still Uniformlogarithmic reductionLow amplitude noise does not influence synchronization behavior1529Typical Synchronizersφ1φ2QQφ1φ2Using delay line2 phase clocking circuit30Cascaded Synchronizers Reduce MTFSync Sync SyncInO1O2Outφ1631ArbitersReq1Req 2Req1Req2Ack1Ack2ArbiterAck1Ack2(a) Schematic symbol(b) ImplementationABReq1Req2ABAck1t(c) Timing diagramVT gapmetastable32PLL-Based SynchronizationDigitalSystemDividerCrystalOscillatorPLLChip 1DigitalSystemPLLChip 2fsystem = N x fcrystalfcrystal,