EE2411UC Berkeley EE241 B. NikolicEE241 - Spring 2002Advanced Digital Integrated CircuitsLecture 29TestUC Berkeley EE241 B. NikolicReferencesl Rabaey, “Digital Integrated Circuits” and EE241 (1998) notesl Chapter 25, Testing of High-Performance Processors by D.K. BhavsarEE2412UC Berkeley EE241 B. NikolicAnnouncementsl Project presentations are in Hogan Room, Cory Hall on Thursday, May 16, 9-12am.l Time per group: 2mins + 6mins x #people + 4mins for discussionl #slides < #minutes for presentationl Project reports and PowerPoint/Acrobat presentations are due at 8am, May 16. No late submissions. l Final exam is in 103 GPB on Wednesday, May 22, 8-11am.UC Berkeley EE241 B. NikolicTest Classificationl Diagnostic test» used in chip/board debugging» defect localizationl “go/no go” or production test» Used in chip productionl Parametric test» x ε [v,i] versus x ε [0,1]» check parameters such as NM, Vt, tp, TEE2413UC Berkeley EE241 B. NikolicChip Debuggingl Design errors or fabrication defects?l Micro-probing the die (1-01.pF)l E-beaml Single-die repair (FIB)UC Berkeley EE241 B. NikolicTesting is Expensivel VLSI testers cost $1-5Ml Volume manufacturing requires large number of testers, maintenancel Tester time costs are in ¢/secl Test cost contributes 20-30% to total chip costEE2414UC Berkeley EE241 B. NikolicTypes of TestingDiagnosisStress, AgeServiceFunctional testSameSystem IntegrationMan. test, transport ShippingManuf. testPhysical defectsManufactureFunctional testDesign flawsPrototype flawsPrototypeDesign ver.Design flawsDesignTest TypeError SourceStepUC Berkeley EE241 B. NikolicFault Models01sa0sa1(output)(input)Most Popular - “Stuck - at” modelx1x2x3Zαβγα, γ : x1 sa1β : x1 sa0 orx2 sa0γ : Z sa1Covers almost all (other) occurring faults, such asopens and shorts.EE2415UC Berkeley EE241 B. NikolicProblem with stuck-at model: CMOS open faultx1x2x1x2ZSequential effectNeeds two vectors to ensure detection!Other options: use stuck-open or stuck-short modelsThis requires fault-simulation and analysis at the switch ortransistor level - Very expensive!UC Berkeley EE241 B. NikolicProblem with stuck-at model: CMOS short fault‘0’‘0’‘0’‘1’CA BDABCDCauses short circuit betweenVdd and GND for A=C=0, B=1Possible approach:Supply Current Measurement (IDDQ)but: not applicable for gigascale integrationEE2416UC Berkeley EE241 B. NikolicDesign for TestabilityM state regsN inputsK outputsK outputsN inputsCombinationalLogicModuleCombinationalLogicModule(a) Combinational function(b) Sequential engine2N patterns 2N+M patternsExhaustive test is impossible or unpracticalUC Berkeley EE241 B. NikolicProblem: Controllability/Observabilityl Combinational Circuits:controllable and observable - relatively easy to determine test patternsl Sequential Circuits: State!Turn into combinational circuits or use self-testl Memory: requires complex patternsUse self-testEE2417UC Berkeley EE241 B. NikolicTest Approachesl Ad-hoc testingl Scan-based Testl Self-TestProblem is getting harder » increasing complexity and heterogeneous combination of modules in system-on-a-chip.» Advanced packaging and assembly techniques extend problem to the board levelUC Berkeley EE241 B. NikolicGenerating and Validating Test-Vectorsl Automatic test-pattern generation (ATPG)» for given fault, determine excitation vector (called test vector) that will propagate error to primary (observable) output » majority of available tools: combinational networks only» sequential ATPG available from academic researchl Fault simulation» determines test coverage of proposed test-vector set» simulates correct network in parallel with faulty networksl Both require adequate models of faults in CMOS integrated circuitsEE2418UC Berkeley EE241 B. NikolicScan-based TestLogicCombinationalLogicCombinationalRegisterRegisterOutInScanOutScanInA BUC Berkeley EE241 B. NikolicPolarity-Hold SRL (Shift-Register Latch)Introduced at IBM and set as company policy (LSSD) System DataSystem ClockScan DataShift A ClockDCSIAL1L2Shift B ClockBQQSOSOEE2419UC Berkeley EE241 B. NikolicScan-Path Flip-FlopSCANININLOADSCAN PHI2 PHI1KEEPOUTSCANOUTUC Berkeley EE241 B. NikolicScan Flip-Flop in AMD K-6EE24110UC Berkeley EE241 B. NikolicScan-based Test —OperationTestScanInTestLatchIn0Out0TestTestLatchIn1Out1TestTestLatchIn2Out2TestTestLatchIn3Out3ScanOutTestφ1φ2N cycles1 cycleevaluationscan-inN cyclesscan-outUC Berkeley EE241 B. NikolicScan TestEE24111UC Berkeley EE241 B. NikolicSelf-test(Sub)-CircuitUnderTestStimulus Generator Response AnalyzerTest ControllerRapidly becoming more important with increasingchip-complexity and larger modulesUC Berkeley EE241 B. NikolicLinear-Feedback Shift Register (LFSR)S0S1S2R R R1 0 00 1 01 0 11 1 01 1 10 1 10 0 11 0 0Pseudo-Random Pattern GeneratorEE24112UC Berkeley EE241 B. NikolicSignature AnalysisRCounterInCounts transitions on single-bit stream ≡ Compression in timeUC Berkeley EE241 B. NikolicBuilt-In Self-TestEE24113UC Berkeley EE241 B. NikolicMemory Self-TestFSMMemory SignatureAnalysisUnder Testdataaddress &R/W control-indata-outPatterns: Writing/Reading 0s, 1s, Walking 0s, 1sGalloping 0s, 1sUC Berkeley EE241 B. NikolicBoundary Scan (JTAG)Printed-circuit boardLogicscan pathnormal interconnectPackaged ICBonding PadScan-inScan-outsi soBoard testing becomes as problematic as chip testingEE24114UC Berkeley EE241 B. NikolicTesting on-chip LogicUC Berkeley EE241 B. NikolicTesting Mixed Analog-Digital