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Berkeley ELENG 241B - Lecture Notes

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1EE241 - Spring 2005Advanced Digital Integrated CircuitsMoWe 2-3:30pm203 McLaughlin2Practical InformationInstructor: Jan M. Rabaey511 Cory Hall , 666-3102, jan@eecsOffice hours: M 3:30-5pm; Reader: Huifang Qin, huifangq@eecsAdmin: Carol Sitea558 Cory Hall, 643-7804, [email protected] Web pagehttp://bwrc.eecs.berkeley.edu/classes/icdesign/ee241_s0523Lecture VideosLectures are videotaped and webcasted:http://webcast.berkeley.eduPlease use the microphones when asking questions!4Class TopicsThis course aims to convey a knowledge of advanced concepts of circuit design for digital LSI and VLSI components in state of the art MOS technologies. Emphasis is on the circuit design, and optimization of either very high speed or low power circuits for use in applications such asmicroprocessors, signal and multimedia processors, communications, memory and periphery. Special attention will devoted to the most important challenges facing digital circuit designers today and in the coming decade, being the impact of scaling, deep sub-micron effects, interconnect, signal integrity, power distribution and consumption, and timing.35EECS141 vs. EECS241EECS 141:Basic transistor and circuit modelsBasic circuit design stylesFirst experiences with design – creating a solution given a number of specsEECS 241:Learning the more advanced techniques Study the challenges facing design in the coming yearsTransistor models of varying accuracyDesign under constraints: power-constrained, flexible, robust,…Creating new solutions to challenging design problems6Special Focus in Spring 2005Design techniques for:Low-power and low-voltage designProcess VariationsRobust DesignPerformance LimitsTiming StrategiesMemory47Class TopicsFundamentals - Technology and modeling – Scaling and limits of scaling (1.5 weeks) Design for deep-submicron CMOS - HIGH SPEED (2.5 weeks)Static CMOS, transistor sizing, buffer design, high-speed CMOS design styles, dynamic logic Design techniques for LOW POWER (2.5 weeks) analysis of power consumption sources power minimization at the technology, circuit, and architecture levelArithmetic circuits – adders, multipliers (2 weeks) Driving interconnect, high-speed signaling (2 weeks) Timing (2 weeks) Timing analysis, flip-flop/latch design, clock skew, clocking strategies, self-timed design, clock generation and distribution, phase-locked loops Memory design (2 week)8Class Organization5 (+/-) assignments1 term-long design projectPhase 1: Proposal (by week 3)Phase 2: Study (report by week 7)Phase 3: Design (presentation and report by final week)Report and presentations last week of classesTake-home final examPresentation at next year’s ISSCC conference or VLSI Circuit Symposium (just kidding, or maybe not)59Class MaterialBaseline: “Digital Integrated Circuits - A Design Perspective”, 2nded. by J. M. Rabaey, A. Chandrakasan, B. NikolićOther reference books:“Design of High-Performance Microprocessor Circuits,” edited by A. Chandrakasan, W. Bowhill, F. Fox“Low-Power Electronics Design,” C. Piguet, Ed.“High-Speed CMOS Design Styles, by K. Bernstein, et al.“Digital Systems Engineering” by W. Dally“Low-Power CMOS Design,” by Chandrakasan and Brodersen“Logical Effort: Designing Fast CMOS Circuits,” by I. Sutherland, B. Sproull, D. Harris10Class MaterialList of background material available on web-siteSelected papers will be made available on web-siteLinked from IEEExplore and other resourcesNeed to be on campus to access, or use library proxy (check http://library.berkeley.edu)Class-notes on web-site611SourcesIEEE Journal of Solid-State Circuits (JSSC)IEEE International Solid-State Circuits Conference (ISSCC)Symposium on VLSI Circuits (VLSI)Other conferences and journals12Project TopicsHigh-performance low-power logic Leakage suppressionCircuit optimization techniquesInterconnect in deep-submicronArithmetic circuitsHigh-speed communicationTiming strategies for gigascale circuitsMemory circuitsOther important circuit topics713ToolsHSPICEYou need an account on cory.eecs0.18 /0.13µm CMOS device models and predictive sub-100nm modelsOther tools, schematic or layout editors are optionalCadence, Synopsys, available on mingus.eecsMore information to be posted on the web-site.14Suggested ReadingChapter 1 – Impact of physical technology on architecture (J.H. Edmondson),Chapter 2 – CMOS scaling and issues in sub-0.25µm systems (Y. Taur)Baseline: Rabaey et al, Chapter 3.Technology roadmap (http://public.itrs.net) - and try to find some contradictionsSelected papers from the web:S. Borkar, “Design challenges of technology scaling,” IEEE Micro, vol.19, no.4, p.23-29, July-Aug. 1999.J. Meindl, “Low Power Microelectronics: Retrospect and Prospect”, Proceedings of the IEEE, April 1995.B. Davari et al., “CMOS Scaling for High Performance and Low Power - The Next Ten Years,” Proceedings of the IEEE, April 1995. A. Masaki, “Deep-Submicron warms up to High Speed Logic,” IEEE Cicuits and Devices Magazine, November 1992.The contributions to this lecture by a number of people (P. Gelsinger, S, Borkhar, etc) are greatly appreciated.815Moore’s Lawz In 1965, Gordon Moore noted that the number of transistors on a chip doubled every 18 to 24 months. z He made a prediction that semiconductor technology will double its effectiveness every 18 months“The complexity for minimum component costs has increased at a rate of roughly a factor of two per year. Certainly over the short term, this rate can be expected to continue, if not to increase. Over the longer term, the rate of increase is a bit more uncertain, although there is no reason to believe it will not remain nearly constant for at least 10 years. That means by 1975, the number of components per integrated circuit for minimum cost will be 65,000.”Gordon Moore, Cramming more Components onto Integrated Circuits, (1965).16Moore’s Law16151413121110987654321019591960196119621963196419651966196719681969197019711972197319741975LOG2 OF THE NUMBER OFCOMPONENTS PER INTEGRATED FUNCTIONElectronics, April 19, 1965.917Transistor Count1,000,000100,00010,0001,0001010011975 1980 1985 1990 1995 2000 2005 2010808680286i386i486Pentium®Pentium®ProK1 Billion 1 Billion TransistorsTransistorsSource: IntelSource: IntelProjectedProjectedPentium®IIPentium®III18Moore’s law and cost1019Moore’s Law in Microprocessors40048008808080858086286386486Pentium® procP60.0010.010.111010010001970 1980 1990 2000 2010YearTransistors


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