1EE241 - Spring 2007Advanced Digital Integrated CircuitsLecture 23: Latches and Flip-Flops2AnnouncementsFinal exam on May 8 in classProject presentations on May 3, 1-5pm23Class MaterialLast lectureSRAMToday’s lectureLatches and flip-flops4Latches: ReadingRabaey et al, Chapters 7 and 10Chapter 10 in Chandrakasan et al, by PartoviStojanovic, Oklobdzija, JSSC 4/9935Latch vs. Flip-Flopz Latchstores data when clock is low DClkQDClkQFlip-Flop (register)stores data when clock rises Clk ClkDDQQ6Latch vs. Flip-FlopCourtesy of IEEE Press, New York. © 200047Latch Pair vs. Flip-FlopPerformance metricsDelay metricsDelay penaltyClock skew penaltyInclusion of logicInherent race immunityPower/Energy MetricsPower/energyPDP, EDPDesign robustness8LatchesNegative latch(transparent when CLK= 0)Positive latch(transparent when CLK= 1)59LatchesDClkClkQClkDClkQTransmission-Gate LatchC2MOS Latch10LatchesCourtesy of IEEE Press, New York. © 2000611TSPC - True Single Phase Clock LogicM1M2M3VDDInOutφφM1M2M3VDDInOutφφM1M2M3VDDInOutφM1M2M3VDDInOutφPrecharged NPrecharged PNon-precharged NNon-precharged P12TSPC - True Single Phase Clock LogicφVDDOutφVDDφVDDφVDDInStaticLogicPUNPDNIncluding logic intothe latchInserting logic betweenlatches713Doubled TSPC LatchesφVDDOutφVDDDoubled n-TSPC latchInφVDDOutφVDDDoubled p-TSPC latch14DEC Alpha 21064Dobberpuhl, JSSC 11/92815DEC Alpha 21064L1:L2:16DEC Alpha 21064Integrating logic into latches• Reducing effective overhead917DEC Alpha 21164L1 LatchL2 LatchL1 Latch with logic18Latch Pair as a Flip-Flop1019Requirements for the Flip-Flop Design• High speed of operation:• Small Clk-Output delay• Small setup time• Small hold time→Inherent race immunity• Low power• Small clock load• High driving capability• Integration of logic into flip-flop• Multiplexed or clock scan• Robustness• Crosstalk insensitivity - dynamic/high impedance nodes are affected20Sources of NoiseCourtesy of IEEE Press, New York. © 20001121Gate IsolationCourtesy of IEEE Press, New York. © 200022Flip-Flop RobustnessRobustness of the storage nodeInput isolationData stored statically, max resistance limitMin capacitance limitPreventing storage node exposure1223Types of Flip-FlopsLatch Pair(Master-Slave)DClkQ DClkQClkDataDClkQClkDataPulse-Triggered LatchL1 L2 L24Flip-Flop Delay z Sum of setup time and Clk-output delay is the true measure of the performance with respect to the system speedz T = TClk-Q+ TLogic+ Tsetup+ TskewD QClkD QClkLogicNTLogicTClk-QTSetup1325Delay vs. Setup/Hold Times050100150200250300350-200 -150 -100 -50 0 50 100 150 200Data-Clk [ps]Clk-Output [ps]Setup HoldMinimum Data-Output26Master-Slave Latch Pairsz Positive setup timesz Two clock phases:» distributed globally» generated locallyz Small penalty in delay for incorporating MUXz Some circuit tricks needed to reduce the overall delay1427Master-Slave Latch PairsCase 1: PowerPC 603 (Gerosa, JSSC 12/94)Vdd VddClkQClkClkbClkbD28T-G Master-Slave Latch•Feedback added for static operation•Unbuffered inputàinput capacitance depends on the phase of the clockàover-shoot and under-shoot with long routesàwirelength must be restricted at the input•Clock load is high•Low power•Small clk-output delay, but positive setup1529Master-Slave LatchesCase 2: C2MOSVddVddVddVddVdd VddVddVddClkCkCkCkCkCkCkbCkbCkbCkbQDFeedback added for static operationLocally generated clockPoor driving capability30Master-Slave TSPC Flip-flopsφVDDDVDDφVDDDφVDDφVDDDVDDφφDφVDDφVDDDVDDφφD(a) Positive edge-triggered D flip-flop (b) Negative edge-triggered D flip-flop (c) Positive edge-triggered D flip-flopusing split-output latches XY1631Pulse-Triggered Latches•First stage is a pulse generatoràgenerates a pulse (glitch) on a rising edge of the clock•Second stage is a latchàcaptures the pulse generated in the first stage•Pulse generation results in a negative setup time•Frequently exhibit a soft edge property•Note: power is always consumed in the pulse generator32Pulsed LatchKozu, ISSCC’96Simple pulsed latch1733Intel/HP Itanium 2Naffziger, ISSCC’0234Pulse-Triggered LatchesHybrid Latch Flip-Flop, AMD K-6Partovi, ISSCC’96VddDClkQQ1835HLFF Operation1-0 and 0-1 transitions at the input with 0ps setup time36Hybrid Latch Flip-FlopPartovi et al, ISSCC’96Skew absorption1937Pulse-Triggered LatchesAMD K-7Courtesy of IEEE Press, New York. © 200038Pulse-Triggered LatchesSemi-Dynamic Flip-Flop (SDFF), Sun UltraSparc III, Klass, VLSI Circuits’98ClkDVdd VddQQPulse generator is dynamic, cross-coupled latch is added for robustness. Loses soft edge on rising transitionLatch has one transistor less in stack - faster than HLFF, but 1-1 glitch existsSmall penalty for adding logic2039Pulse-Triggered Latches7474, from early 1960’sClkDQQSR40Pulse-Triggered LatchesFirst stage is a sense amplifier, precharged to high, when Clk = 0After rising edge of the clock sense amplifier generates the pulse on S or RThe pulse is captured in S-R latchCross-coupled NAND has different propagation delays of rising and falling edgesCase 4: Sense-amplifier-based flip-flop, Matsui 1992.DEC Alpha 21264, StrongARM 1102141Sense Amplifier-Based Flip-FlopCourtesy of IEEE Press, New York. © 200042Flip-Flop Performance ComparisonTotal power consumedinternal powerdata power clock powerMeasured for four casesno activity (0000… and 1111…)maximum activity (0101010..)average activity (random sequence)Test benchDelay is (minimum D-Q)Clk-Q + setup timeClkDataClock50fF200fF200fFDQQStojanovic, Oklobdzija JSSC 4/992243Flip-Flop Performance Comparison010203040506070100 150 200 250 300 350 400 450 500Delay [ps]Total power [uW] mSAFFSDFFHLFFC2MOSTG M-SOriginal SAFF44Sampling Window ComparisonNaffziger, JSSC 11/022345Local Clock GatingDQCKICKIB0.85 0.8520.850.5 0.50.51.2CP0.50.85 0.50.85XNORCKIBCKICKIB0.50.50.850.5PulseGeneratorData-TransitionLook-AheadDI‘Clock on demand’Flip-flop46Next
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