1EE241 - Spring 2005Advanced Digital Integrated CircuitsLecture 7:Logic Families for Performance2AdminHomeworks due on We. New assignment on your way.Will get feedback on the projects within a week.23Logical Effort: SummaryD = DH+ Pd = h + pDelaypIntrinsic DelayN1Number of StageshEffort DelayH = FGBh = fgEffortn/aBranching Effortf = Cout/CinElectrical Effort (Fanout)gLogical EffortPathStage∏=igGinoutCCF /=∏=ibB∑=iHhD∑=ipP4Increasing PerformanceScaling technologyCircuit/logic level:1. Logic optimizations2. Transistor sizing, buffering3. Wire optimization, repeaters4. Supply voltage5. Threshold voltage6. Logic styles7. Timing, latchesMicroarchitecture level35Design TechniquesPerformance does not come for freePerformanceDesignEffortASIC/RTL‘Enhanced’ ASICStructured ASICCustom designDynamic custom6RTL Design FlowRTLSynthesisHDLnetlistlogicoptimizationnetlistLibraryphysicaldesignlayoutabsq01dclkabsq01dclkModuleGeneratorsManualDesign[from K. Keutzer]47RTL/ASIC DesignDesign description in Verilog/VHDL RTLSynthesized logicStandard cellsPre-defined macrosStatic timing verification, pre- and post-layoutStatistical vs. extracted wire loadsPhysical designTop-level floorplanAutomatic place and routeClock tree synthesizedPost layout optimization, verification8Logic OptimizationPerform a variety of transformations and optimizationsStructural graph transformationsBoolean transformationsMapping into a physical librarysmaller, fasterless powerlogicoptimizationnetlistnetlistLibraryabsq01dclkabsq01dclk[from K. Keutzer]59Combinational Logic OptimizationInput: • Initial Boolean network• Timing characterization for the module- input arrival times and drive factors- output loading factors• Optimization goals- output required times• Target library descriptionOutput:• Minimum-area netlist of library gates which meets timing constraintsA very difficult optimization problem ![from K. Keutzer]10Logic OptimizationlogicoptimizationnetlistnetlistLibrarytechindependenttechdependent2-levelLogic optmultilevelLogic optRealLibraryGenericLibrary[from K. Keutzer]611Modern Approach to Logic OptimizationDivide logic optimization into two subproblems:• Technology-independent optimization- determine overall logic structure- estimate costs (mostly) independent of technology- simplified cost modeling• Technology-dependent optimization (technology mapping)- binding onto the gates in the library- detailed technology-specific cost modelOrchestration of various optimization/transformation techniques for each subproblem12Logic Level OptimizationsRRLogic DepthorTechniques: Restructuring, pipelining, retiming, technology mappingWell covered by today’s logic and sequential synthesis713Logic Optimizations (2)Technique: Removal of common sub-expressionStart from tree structure/outputFanoutTp = O(FO) also effects wiring capacitanceLate arriving14Technology mapping13579fan-in0.01.02.03.04.0tp(nsec)tpHLtptpLHlinearquadraticAVOID LARGE FAN-IN GATES! (Typically not more than FI < 4)Tp= O(FI2) !Observation: only true if FItranslates in series devices -otherwise lineare.g. NAND pull-downNOR pull-upFanin815Technology Mapping for PerformanceAlternative coveringsUse low FI modules on critical path(s)Library composition?16CMOS Logic StylesCMOS tradeoffs:SpeedPower (energy)AreaDesign tradeoffsRobustness, scalabilityDesign timeMany styles: don’t try to remember the names –remember the principlesChanging the logic style – can it be done without breaking the synthesis flow?917CMOS Logic StylesPUNPDNABCOUTVDDGNDABCComplementaryrobustscaleslarge and slowLOGICNETWORKABCOUTPass Transistor Logicsimple and fastnot always very efficientversatile18CMOS Logic StylesLOADABCPDNOUTGNDGNDVDDRatioed Logicsmall & faststatic powerRPDN <<RLOADVDDPDNφIn1In2In3OutφCLDynamic LogicSmall & fastest!Noise issuesScales?1019OthersCurrent-mode logicAdiabatic logic20Pulsed Static CMOSRH – Reset highRL – Reset lowFast pull-upFast pull-downChen, Ditlow, US Pat. 5,495,188 Feb. 1996.1121PS-CMOSEvaluation and reset waves: reset is 1.5x slower22PS-CMOSAdvantages:No dynamic nodes – good noise immunityReset delay slower than evaluationNo data dependent delay (worst case gets better)No false transitionsDisadvantagesWidth of reset wave limits logic depthMargin in design1223Skewing GatesDifferent rising and falling delaysWWLE = 24Skewing Gates4WWLE =1325Ratioed LogicVDDVSSPDNIn1In2In3FRLLoadVDDVSSIn1In2In3FVDDVSSPDNIn1In2In3FVSSPDNResistiveDepletionLoadPMOSLoad(a) resistive load (b) depletion load NMOS (c) pseudo-NMOSVT < 0Goal: to reduce the number of devices over complementary CMOS26Pseudo-NMOS0.0 0. 5 1.0 1.5 2.02.50.00.51.01.52.02.53.0Vin, VVout, VW/Lp = 4W/Lp = 2W/Lp = 1W/Lp = .25W/Lp = 0.5VDDIn1In2In3FPMOSloadPDNTrade-off between performance and power + noise margins1427Differential Logic28Differential LogicDifferential Cascode Voltage Switch (DCVS)Differential Split-Level Logic (DSL)Regenerative Push-Pull Cascode Logic (PPCL)Pass transistor logic familiesDynamic logic families1529Differential Logic+ implicit invert, higher logic density30Cascode Voltage Switch LogicVDDVSSPDN1OutVDDVSSPDN2OutAABBM1 M2Cascode Voltage Switch Logic (CVSL)Sometimes called Differential Cascode Voltage Switch Logic (DCVSL)1631CVSLA B M1M2A B0 0.2 0.4 0.6 0.8 1.0-0.50. 51. 52. 5Time, nsVol tage,VOutOutA,BA,BM3M4OutOutVDD-VthFast (but hysteresis due to latch function)No static power dissipationBUT: large cross-over current!32CVSLFull adder designHow to design for reduced transistor count?1733Karnaugh Map Technique34Karnaugh Map Technique0100 01 11 10x1x2x300001111Build sharedcubes first!Add other cubes nextLOADx1x3x1x3x2x2QQLOADx1x3x1x3x2x2QQx1x21835ExampleQ = x1x2x3x4+ x1(x2+x3+x4)36Push-Pull Cascode LogicGieseke et al, U.S. Patent 5,023,480 June 1991.1937DSL Differential Split-Level Logic38Simulation Results for Different Adders2039Pass-Transistor LogicInputsSwitchNetworkOutOutABBB• N transistors• No static consumptionABBF = AB0• Transistor implementation using NMOS40Pass-Transistor LogicPerformance of PTL:Advantage over CMOS in implementing XOR, MUXDisadvantage in implementing AND, OR.Datapaths, arithmetic circuits are examples of use:Adders and multipliers use XOR, MUXAdvantage of complementary implementationComparisons:When a new logic family is introduced, the examples are chosen to show its advantages; (not disadvantages).Comparison papers sometimes point to the disadvantagesFull-custom design2141Examples of PTL StylesComplementary Pass-Transistor