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Berkeley ELENG 241B - lecture 26 - Links

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EE2411UC Berkeley EE241 B. NikolicEE241 - Spring 2002Advanced Digital Integrated CircuitsLecture 26High-Speed LinksBased on materials by M. Horowitz, S. SidiropoulosUC Berkeley EE241 B. NikolicAnnouncementsl No class, office hour on Tuesday, May 7.» Class will be pre-taped on May 6, 12:30-2pml Homework #5 due on May 7l Last lecture is on May 14l Project presentations are on May 16, 9am-12pm, in BWRCl Final exam is in 103 GPB, Wednesday, May 22, 8-11amEE2412UC Berkeley EE241 B. NikolicReadingl Chapter 19, High-Speed Inter-Chip Signaling, by Sidiropoulos, Yang, Horowitzl Digital Systems Engineering, by W.J. Dally and J.W. Poulton, Cambridge’98UC Berkeley EE241 B. NikolicTerminationsOff- versus On-chip TerminationsShould be linear and process, supply-voltage and temperature independentEE2413UC Berkeley EE241 B. NikolicFET TerminationsIV-characteristicof two-element resistor[Dally]UC Berkeley EE241 B. NikolicPass-gate Style TerminationEE2414UC Berkeley EE241 B. NikolicAdjustable TerminatorsThermometer-codedAdjustmentsReduces switch-noiseUC Berkeley EE241 B. NikolicLink Issuesl Signaling: sending and receiving the informationl Clocking: Determining which bit is whichRxTxRTERMChannelRTERMtbit/21 0 0 01 01EE2415UC Berkeley EE241 B. NikolicTransmitter Designl Critical components: Sync, Mux, Txl Design issues:» Slew rate control vs ISI, jitter» Output current and impedance controll Clock and Driver power dissipationData Generation Pre-Driver DriverTx50ΩSyncMuxEncoderUC Berkeley EE241 B. NikolicTransmitter Frequency Limitsl Max clock frequency > 8-FO4 (I.e. 1-GHz @ 0.25u)l Faster links should use multiple clocks:» Critical on mux/demux2.5 3.5 4.5 5.50.010.020.030.040.050.060.0Clock pulse width (FO-4)Pulse amplitude reduction %EE2416UC Berkeley EE241 B. NikolicSimple Transmitterl DDR: send a bit per clock edgel Critical issues: » 50% duty cycle» Tbit > 4-FO4Data_OData_E1 2 3 4 50102030bit time (normalized to FO4)output pulse width closure (%)UC Berkeley EE241 B. NikolicFastest Transmitter» Off chip time constant smaller than on chip:Þ Generate current pulse at the output» Limited only by the output capacitanceoutout_bRTERMRTERMx 8d0d0ck3D0 D1 D2data(ck0)clock(ck3)0.50 0.60 0.70 0.80 0.90 1.000.010.020.030.0Bit-width (#FO-4)% eye closure» Limiting time constant 25-Ω*Cpad» Cpad = 8*Cdriver + CesdEE2417UC Berkeley EE241 B. NikolicSimple Receiverl Preconditioning stage: filter/integrate rectify CMl Latch makes decision (4-FO4)l DAC can be used to compensate offsetsinrefclkAlatchD/AclkUC Berkeley EE241 B. NikolicFastest Receiverl Use multiple input receivers» Simplest 2, more complex 4-8» Decouples Tbit from latch resolution» Leverage high input impedance amplifiersD0 D1 D2 D7clk0clk1clk2clk3Ring Oscillatorclk0 clk1 clk2 clk3ck0ck1ck2ck3ck4dinTo AmplifiersEE2418UC Berkeley EE241 B. NikolicGenerating the Sample ClockTwo options:l Send clock with data» Hope that wire delays matchl Extract clock from data» Use data transitionsl PLL/DLL» Uses feedback» Adj phase of int clk» Many different designs– Delay line based– VCO basedDLLclkref clkdatarefref clkD0 D1 D2 D3dataclkUC Berkeley EE241 B. NikolicDual-Loop PLLPD/CPFSMPDinCLKC0CΠCLKDCAB0BΠ0o30o60o90o120o150oφ-Iφψφ’ψ’AMPCLK BUFrefCLK+PERIPHERALDLLCORE DLLΘEE2419UC Berkeley EE241 B. NikolicSilicon Trends l Scaling» Vdd scales, transistors get smaller» Idsat/µ stays constant» Gates get fasterl Speed: should scale with technologyl Power: » For constant output current– Device size roughly constant– Output capacitance roughly constantl Output current constant, on-chip power scalesl Pretty picture, but...UC Berkeley EE241 B. NikolicProblem #1: Silicon Is Not Ideall Noise: » Both on timing and signaling» Both AC and DCl Timing noise:» AC: jitter (scales with process), DC: offset (does not)l Signaling noise:» AC (two kinds: proportional to swing and uncorrelated)» DC offsets (do not scale but are correctable)Time ReferenceEE24110UC Berkeley EE241 B. NikolicDC Timing Offset Compensationl E.g.: Third generation Rambus DRAM Clocking» Offsets compensated once at boot time and stay VT independent through bias tracking» Main limitation is PC boot timeMixer Clk BufAmpPh.Det.CTMup/dnCNTDecoder8AdderDecoderMixer Clk BufAmp888FromCore DLLFromCore DLLTOFFSFbClkCore DLLCTMCTM8TCLKTOFFSPeripheral T-DLLCFMRCLKROFFSPeripheral R-DLL8UC Berkeley EE241 B. NikolicOffset Compensation Linearity0 64 128 192Offset Register Value090180270360Phase Offset (degrees)400 MHz533 MHz255» Digital-to-time converter is better than 5-bits accuracyEE24111UC Berkeley EE241 B. NikolicProblem #2: Channel Is NOT Ideal» At high frequencies– Wires have loss– Packages have crosstalk– ESD becomes important– Si-substrate losses non-negligible100MHz 1GHz 10GHz-21.0-15.0-9.0-3.06m H(s)12m H(s)UC Berkeley EE241 B. NikolicOther Channel Non-Idealitiesl Image currents are largel High density IO may dictate pseudo-differentiall AC-ground impedance is worse at HF» A lot of vias close to packageá Small system voltage margins» Systems shipping in volume with <10-15% margininrefCINCREFVssLpinLpinRdrvRdrvEE24112UC Berkeley EE241 B. NikolicSolution: Use Signal Processingl Modems have been using it forever..l True random noise is really smalll Deterministic noise is what degrades margins» Figure out where the noise is coming from and cancel itl ISI is frequency dependent attenuationl Crosstalk is data dependent couplingUC Berkeley EE241 B. NikolicEqualization Examplel ZFE: Transmitter Tx(s) is approx 1/Ch(s)0.0 0.3 0.6 0.9 1.2-0.3-0.10.10.30.50.7UnequalizedEqualization PulseEnd of Cabletime (ns)VoltageEE24113UC Berkeley EE241 B. NikolicMore Signal Processingl Get multiple bits/Hz:» Step-1: – Simultaneous bi-directionalVlinedrvVrefVrefH (shared)VrefL (shared)rcvrreceive signaltransmit signalVlineVref(Vline - Vref)+ve-veVrefHVrefLUC Berkeley EE241 B. NikolicSimultaneous Bidirectional Eyesvoltagemargintiming margin timing margin*Transmit signal & receive signal in quadrature phaseFixed VrefL= Vdd – 1.5*VswingEE24114UC Berkeley EE241 B. NikolicMore Bits/Hzl Multi-level signaling (aka PAM)» Convert extra voltage margin to more bitsl For constant bits/sec» 1/2 Tsymbol» 1/3 Vmargin» Real problem is that we rarely have enough marginÜ Need even more signal processingUC Berkeley EE241 B. NikolicElectrostatic Discharge (ESD)l IC handling environment can generate voltages of 5kV (humid) or 35kV (dry)l Industry standard stress tests:» Human body


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