DOC PREVIEW
Berkeley ELENG 241B - Homework

This preview shows page 1 out of 2 pages.

Save
View full document
View full document
Premium Document
Do you want full access? Go Premium and unlock all 2 pages.
Access to all documents
Download any document
Ad free experience
Premium Document
Do you want full access? Go Premium and unlock all 2 pages.
Access to all documents
Download any document
Ad free experience

Unformatted text preview:

EE241 Advanced Digital Integrated Circuits Spring 2000. HOMEWORK 4. Due: Tuesday, April 11, 2000 at 5pm in 558 Cory This is an individual assignment! 1. Transmission lines. Assume VDD=1.5V, using 0.25µm class technology. VDDCL=0.2PFinVDDL=350nH/mC=150pF/m10cmVsVL Figure 1: Transmission line. a) The Figure 1 shows an output driver feeding a 0.2 pF effective fan-out of CMOS gates through a transmission line. Size the two transistors of the driver to optimize the delay. Sketch waveforms of VS and VL, assuming a square wave input. Label critical voltages and times. b) Size down the transistors by m times (m is to be treated as a parameter). Derive a first order expression for the time it takes for VL to settle down within 10% of its final voltage level. Compare the obtained result with the case where no inductance is associated with the wire. Please draw the waveforms of VL for both cases, and comment. c) Use the transistors as in part a). Suppose CL is changed to 20PF. Sketch waveforms of VS and VL, assuming a square wave input. Label critical voltages and times. d) Assume now that the transmission line is lossy. Perform Hspice simulation for three cases: R=100 Ω/cm; R=2.5 Ω/cm; R=0.5 Ω/cm. Get the waveforms of VS, VL and the middle point of the line. Discuss the results.2. Delay line. DnDn’Dn+1’Dn+1RRVc Figure 2: Differential delay element. Design a delay line composed of the differential delay element pairs from Figure 2. a) Set VDD=1.5V, and the differential signal swing = 1 V. Please design a delay element pair with 1ns delay, by sizing the transistors, choosing appropriate values for R and Vc. b) Design an adjustable resistor for the above delay element. c) Derive a first-order expression for the supply sensitivity and run a simulation to verify the result. 3. Ling adder Read the article “A sub-nanosecond 0.5µm 64 b adder design,” by S. Naffziger presented at 1996 IEEE International Solid-State Circuits Conference, Digest of Technical Papers, pp. 362-363. a) Reconstruct the key logic equations in the design of this adder. b) List the four key items that result in speed performance of this


View Full Document
Download Homework
Our administrator received your request to download this document. We will send you the file to your email shortly.
Loading Unlocking...
Login

Join to view Homework and access 3M+ class-specific study document.

or
We will never post anything without your permission.
Don't have an account?
Sign Up

Join to view Homework 2 2 and access 3M+ class-specific study document.

or

By creating an account you agree to our Privacy Policy and Terms Of Use

Already a member?