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Berkeley ELENG 241B - Lecture 1 - intro

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EE2411UC Berkeley EE241 B. NikolicEE241 - Spring 2000Advanced Digital Integrated CircuitsTu-Th 2:00 – 3:30pm203 McLaughlinUC Berkeley EE241 B. NikolicPractical Informationl Instructor: Borivoje Nikolic570 Cory Hall , 3-9297, [email protected] hours: TuTh 3:30-5:00pml TA: TBAl Admin: Alev Burton - 558 Cory Halll Class Web pagehttp://www-inst.eecs.berkeley.edu/~ee241EE2412UC Berkeley EE241 B. NikolicClass Organizationl +/- 5 assignmentsl 1 term-long design project» Phase 1: Proposal (by week 3)» Phase 2: Study (report by week 7)» Phase 3: Design (presentation and report by final week)l Take-home FinalUC Berkeley EE241 B. NikolicClass Materiall No textbookl Must be familiar with “Digital Integrated Circuits - A Design Perspective”, by J. M. Rabaeyl Other reference books:» “High-Speed CMOS Design Styles, by K. Bernstein, et al.» “Digital Systems Engineering” by W. Dally» “High-Performance System Design: Circuits and Logic,” by V.G. Oklobdžija» “Low-Power CMOS Design,” by Chandrakasan and BrodersenEE2413UC Berkeley EE241 B. NikolicClass Materiall List of background material available on web-sitel Selected papers will be made available on web-site» Protected areal Papers on http://www.melvyl.ucop.edul Class-notes on web-siteUC Berkeley EE241 B. NikolicSourcesl IEEE Journal of Solid-State Circuits (JSSC)l IEEE International Solid-State Circuits Conference (ISSCC)l Symposium on VLSI Circuits (VLSI)l Other conferences and journalsEE2414UC Berkeley EE241 B. NikolicClass Topicsl This course aims to convey a knowledge of advanced concepts of circuit design for digital LSI and VLSI components in state of the art MOS technologies. Emphasis is on the circuit design, optimization, and layout of either very high speed, high density or low power circuits for use in applications such as micro-processors, signal and multimedia processors, memory and periphery. Special attention will devoted to the most important challenges facing digital circuit designers todayand in the coming decade, being the impact of scaling, deep sub-micron effects, interconnect, signal integrity, power distribution and consumption, and timing. l SPECIAL FOCUS in SPRING 2000:» high-performance low -power logic (as needed for digital radio)» interconnect» timing» arithmetic circuits» memoryUC Berkeley EE241 B. NikolicClass Topicsl Fundamentals - Technology and modeling - Design Tolerances – Limits of scaling (1 week) l Design for deep-submicrondevices - HIGH SPEED (2 weeks)» transistor sizing, buffer design, bootstrapping, reduced swing l Design techniques for LOW POWER (2 weeks) » analysis of power consumption sources » power minimization at the technology, circuit, and architecture levell Arithmetic circuits – adders, multipliers (2 weeks) l Impact of interconnect (2 weeks) l Timing (2 weeks) » Clock skew, Clocking strategies, Self-timed design , arbiters / phase-locked loops l Memory design (2 week) l Design of array structures (1 week) » FPGAs and reconfigurable logic l Design for test (1 week)EE2415UC Berkeley EE241 B. NikolicProject Topicsl High-performance low-power logic (radio)l Low voltage designl Interconnect in deep-submicronl Arithmetic circuitsl High-speed communicationl Timing of gigascale circuitsl Reconfigurable logicl Reliability of deep-submicron circuits l Embedded DRAM and/or flashl Other important circuit topicsUC Berkeley EE241 B. NikolicMoore’s LawIn 1965, Gordon Moore noted that the number of transistors on a chip doubled every 18 to 24 months. He made a prediction that semiconductor technology will double its effectiveness every 18 monthsEE2416UC Berkeley EE241 B. NikolicMoore’s Law16151413121110987654321019591960196119621963196419651966196719681969197019711972197319741975LOG2 OF THE NUMBER OFCOMPONENTS PER INTEGRATED FUNCTIONElectronics, April 19, 1965.UC Berkeley EE241 B. NikolicTransistor Count1,000,000100,00010,0001,0001010011975 1980 1985 1990 1995 2000 2005 2010808680286i386i486Pentium®Pentium®ProK1 Billion TransistorsSource: IntelProjectedPentium® IIPentium® IIIEE2417UC Berkeley EE241 B. NikolicProcessor Frequency Trend386486Pentium(R)Pentium Pro(R)Pentium(R) IIMPC750604+604601, 60321264S2126421164A2116421064A21066101001,00010,0001987198919911993199519971999200120032005Mhz110100Gate Delays/ ClockIntelIBM Power PCDECGate delays/clockProcessor freq scales by 2X per generationÊ Frequency doubles each generationË Number of gates/clock reduce by 25%V.De, S. BorkarISLPED’99UC Berkeley EE241 B. NikolicTechnology Scalingl Goals of scaling the dimensions by 30%:» Reduce gate delay by 30% (increase operating frequency by 43%)» Double transistor density» Reduce energy per transition by 65% (50% power savings @ 43% increase in frequencyl Technology generation spans 2-3 years, but µP speed doubles every generation (not increased only by 43%)S. Borkar, IEEE Micro, July 1999.EE2418UC Berkeley EE241 B. NikolicTotal Transistor WidthTransistors scale by ~ 30% per generationSource: IntelPentium II (R)Pentium (R)Pentium (R)Pentium MMX (TM)Pentium II (R)Pentium Pro (R)Pentium MMX (TM)Pentium MMX (TM)Pentium (R)Pentium MMX(TM)Pentium (R)Pentium II (R)Pentium Pro (R)Pentium II (R)1101003 4 5 6 7 8Process Technology GenerationTransistor Size (meters)Total TransistorAverage TransistorUC Berkeley EE241 B. NikolicTechnology Evolution (1997 data)National Technology Roadmap for Semiconductors17000100006000350021001250750Max frequency [MHz],Local1831751701601309070Max µP power [W]1098-97-876-76Metal layers0.40.5-0.60.6-0.90.9-1.21.2-1.51.5-1.81.8-2.5Supply [V]25355070100140200Channel length [nm]2014201120082005200219991997Year of Introductionhttp://www.sematech.orgEE2419UC Berkeley EE241 B. NikolicTechnology RoadmapUC Berkeley EE241 B. NikolicMoore’s Law – Logic DensityA. Masaki, 1992.IEEE Circuits & DevicesEE24110UC Berkeley EE241 B. NikolicMoore’s Law - Logic Densityhrinks and compactions meet density goalsew micro-architectures drop density Source: IntelPentium (R)Pentium Pro (R) 486386i86011010010001.5µ1.0µ0.8µ0.6µ0.35µ0.25µ0.18µ0.13µLogic Density2x trendLogic Transistors/mm2Pentium II (R) UC Berkeley EE241 B. NikolicInterconnect Scaling TrendsMinimum Widths (Relative)0.00.51.01.52.02.53.03.51.0µ 0.8µ 0.6µ 0.35µ 0.25µM5M4M3M2M1PolyMinimum Spacing (Relative)0.00.51.01.52.02.53.03.54.01.0µ 0.8µ 0.6µ 0.35µ 0.25µM5M4M3M2M1PolyInterconnect Stack0123456789101.0µ 0.8µ 0.6µ 0.35µ 0.25µM5ILD4M4ILD3M3ILD2M2ILD1M1ILD0PolyField


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