EE2411UC Berkeley EE241 B. NikolicEE241 - Spring 2002Advanced Digital Integrated CircuitsLecture 22TimingUC Berkeley EE241 B. NikolicLatch vs. Flip-Flopl Latchstores data when clock is low DClkQDClkQl Flip-Flopstores data when clock rises Clk ClkDDQ QEE2412UC Berkeley EE241 B. NikolicLatch vs. Flip-FlopCourtesy of IEEE Press, New York. 2000UC Berkeley EE241 B. NikolicLatch Pair vs. Flip-Flopl Performance metricsl Delay metrics» Delay penalty» Clock skew penalty» Inclusion of logic» Inherent race immunityl Power/Energy Metrics» Power/energy» PDP, EDPl Design robustnessEE2413UC Berkeley EE241 B. NikolicLatchesNegative latch(transparent when CLK= 0)Positive latch(transparent when CLK= 1)UC Berkeley EE241 B. NikolicLatchesDClkClkQClkDClkQTransmission-Gate LatchC2MOS LatchEE2414UC Berkeley EE241 B. NikolicLatchesCourtesy of IEEE Press, New York. 2000UC Berkeley EE241 B. NikolicPipelined Logic using C2MOS InFOutφφVDDφφVDDφφVDDC2C1GC3NORA CMOSWhat are the constraints on F and G?EE2415UC Berkeley EE241 B. NikolicTSPC - True Single Phase Clock LogicM1M2M3VDDInOutφφM1M2M3VDDInOutφφM1M2M3VDDInOutφM1M2M3VDDInOutφPrecharged NPrecharged PNon-precharged NNon-precharged PUC Berkeley EE241 B. NikolicTSPC - True Single Phase Clock LogicφVDDOutφVDDφVDDφVDDInStaticLogicPUNPDNIncluding logic intothe latchInserting logic betweenlatchesEE2416UC Berkeley EE241 B. NikolicDoubled TSPC LatchesφVDDOutφVDDDoubled n-TSPC latchInφVDDOutφVDDDoubled p-TSPC latchUC Berkeley EE241 B. NikolicMaster-Slave TSPC Flip-flopsφVDDDVDDφVDDDφVDDφVDDDVDDφφDφVDDφVDDDVDDφφD(a) Positive edge-triggered D flip-flop (b) Negative edge-triggered D flip-flop (c) Positive edge-triggered D flip-flopusing split-output latches XYEE2417UC Berkeley EE241 B. NikolicDEC Alpha 21064Dobberpuhl, JSSC 11/92UC Berkeley EE241 B. NikolicDEC Alpha 21064L1:L2:EE2418UC Berkeley EE241 B. NikolicDEC Alpha 21064Integrating logic into latches• Reducing effective overheadUC Berkeley EE241 B. NikolicDEC Alpha 21164L1 LatchL2 LatchL1 Latch with logicEE2419UC Berkeley EE241 B. NikolicLatch Pair as a Flip-FlopUC Berkeley EE241 B. NikolicRequirements in the Flip-Flop Design• High speed of operation:• Small Clk-Output delay• Small setup time• Small hold time→Inherent race immunity• Low power• Small clock load• High driving capability• Integration of the logic into flip-flop• Multiplexed or clock scan• Robustness• Crosstalk insensitivity - dynamic/high impedance nodes are affectedEE24110UC Berkeley EE241 B. NikolicSources of NoiseCourtesy of IEEE Press, New York. 2000UC Berkeley EE241 B. NikolicGate IsolationCourtesy of IEEE Press, New York. 2000EE24111UC Berkeley EE241 B. NikolicFlip-Flop Robustnessl Robustness of the storage nodel Input isolationl Data stored statically, max resistance limitl Min capacitance limitl Preventing
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