1EE241 - Spring 2005Advanced Digital Integrated CircuitsLecture 8:Logic Families for PerformancePTL and Dynamic2AdminHomework due today. New assignment on your way.Should have received feedback on projects. Please submit revised abstract by Monday morning.23Pass-Transistor LogicInputsSwitchNetworkOutOutABBB• N transistors• No static consumptionABBF = AB0• Transistor implementation using NMOS4Pass-Transistor LogicPerformance of PTL:Advantage over CMOS in implementing XOR, MUXDisadvantage in implementing AND, OR.Datapaths, arithmetic circuits are examples of use:Adders and multipliers use XOR, MUXAdvantage of complementary implementationComparisons:When a new logic family is introduced, the examples are chosen to show its advantages; (not disadvantages).Comparison papers sometimes point to the disadvantagesFull-custom design35Examples of PTL StylesComplementary Pass-Transistor LogicNMOS-only pass-transistor networkTransmission-gate logicNMOS+PMOS pass gatesDouble Pass-Transistor LogicNMOS+PMOS network Numerous other logic families6NMOS-only switchA =2.5V BC = 2.5VCLA = 2.5 VC = 2.5 VBM2M1MnThreshold voltage loss causes static power consumption00.511.520.01.02.03.0Time, nsVoltage, VxOutIn47SolutionsTransmission gates – adding complexity Low-threshold switches – leakage!Level-restorationM2M1MnMrOutABVDDVDDLevel RestorerX8Single-Ended Level RestoringOutputInputFeedback InverterOutput InverterLevel RestorationTransistor59Differential Level RestoringDifferential NMOS Logic Treef fInputsInputsDifferent level restoration leads to different logic families10Different Restoration SchemesDifferential NMOS Logic TreeffInputsInputsSwing-Restored Pass-Transistor LogicParameswar, et alCICC’94, JSSC 6/96611Other Level-Restoring SchemesDifferential NMOS Logic TreeffInputsInputsDifferential NMOS Logic TreeffInputsInputsEnergy Economized Pass-TransistorLogicDCVS with Pass Gates(DCVS-PG)12Pass-Transistor Logic Families713CPL Complementary Pass-Transistor Logic (CPL)Yano et al, CICC’89, JSSC 4/90 • Complementary functions• Reduced number of logic levels• Less transistors than CMOS • Fast – reduced load• Complementary inputs – complementary outputs• VTdrop – several solutions14CPLSame topology of networksJust different signal arrangements815Complementary Pass-Transistor Logic (CPL)AAS SA ABBCCSS(a)(b)BBQQbn1 n2n4n3XORSumnFET logicnetwork-Fast-VTdrop- Efficientimplementationof arithmetic16CPL Karnaugh MapsAB000 1C1C2AABABA⋅C2C1AABBA⋅C2C1917CPL vs. CMOS18Skewing Output Inverter1019Differential vs. Single-Ended20Double Pass-Transistor Logic (DPL)ABABBAVDDBAOOABABBABAOOBABABABAABABAND/NANDXOR/XNOR1121Comparison of Logic StylesZimmermann, Fichtner, JSSC 7/9722Comparison of Logic Styles1223Comparison of Logic Styles24Results1325Results26Results1427Dynamic LogicMpMeVDDPDNφIn1In2In3OutMeMpVDDPUNφIn1In2In3φφOutCLCLφp networkφn network2 phase operation:• Evaluation • Precharge• N + 1 Transistors• Ratioless• No Static Power Consumption• Noise Margins small (NML)• Requires Clock28Dynamic GatesNMOS InverterPMOS InverterCourtesy of IEEE Press, New York. © 2000See Bowhill, Chapter 7.1529Dynamic LogicAdvantages:FastCompactDisadvantages:Less robust (noise margins, sensitive to leakage, noise coupling, charge sharing)Needs clock30Logical EffortLE =φφInOut1631Logical EffortLE =φφOutLE =φφOut32Charge LeakageCourtesy of IEEE Press, New York. © 2000ILeak= (IN sub+ IN diode) – (IP sub+ IP diode)Time to switch the next gate: tsw= (CDYN* Vsw)/ILeakLimits the minimum frequency:fmin= 1/(tsw* #phases per clk cycle)1733Compensating Leakage34Charge Sharing (Redistribution)MpMeVDDφOutφAB = 0CLCaCbMaMbXCLVDDCLVoutt()CaVDDVTnVX()–()+=or∆VoutVoutt()VDD–CaCL--------VDDVTnVX()–()–==∆VoutVDDCaCaCL+----------------------⎝⎠⎜⎟⎛⎞–=case 1) if ∆Vout < VTncase 2) if ∆Vout > VTn1835Charge Sharing - SolutionsMpMeVDDφOutφABMaMbMblMpMeVDDφOutφABMaMbMbl(b) Precharge of internal nodesφ(a) Static bleeder36Aside: Dynamic LatchCourtesy of IEEE Press, New York. © 20001937Charge SharingA,B = 0DYN prechargedCharge sharing ifSEL togglesCourtesy of IEEE Press, New York. © 200038Aside: Noise in ICsSources of noiseCouplingDevice couplingCapacitive coupling between wiresInductive couplingSupply line bounceCharge InjectionFrom substrateα-particlesRobustness of a circuitNoise marginsSensitivity to noise2039Clock FeedthroughMpMeVDDφOutφAB CLCaCbMaMbXφ2.5Vovershootout40Miller and Back-gate CouplingCourtesy of IEEE Press, New York. © 2000ClockFeedThrough(or Miller)Back-gate coupling2141Capacitive CouplingCourtesy of IEEE Press, New York. © 200042Capacitive CouplingDynamic node:Static node:Courtesy of IEEE Press, New York. © 20002243Capacitive CouplingCourtesy of IEEE Press, New York. © 2000Lateral coupling:Shielding44Minority Charge InjectionCourtesy of IEEE Press, New York. © 20002345Supply NoiseCourtesy of IEEE Press, New York. © 200046Cascading Dynamic GatesMpMeVDDφφMpMeVDDφφInOut1Out2φOut2Out1InVt∆VVTn(a)(b)Only 0→1 Transitions allowed at inputs!2447Cascading Dynamic Logic48Domino LogicMpMeVDDPDNφIn1In2In3Out1φMpMeVDDPDNφIn4φOut2MrVDDStatic Inverterwith Level RestorerKrambeck et al, JSSC 6/822549Logical EffortLE =φφInOutInverter pair:Skewed inverter pair:50Logical EffortLE =φφOut2651Domino Logic - Characteristics• Only non-inverting logic• Very fast - Only 1->0 transitions at input of invertermove VM upwards by increasing PMOS• Adding level restorer reduces leakage andcharge redistribution problems• Optimize inverter for fan-out52Designing with Domino LogicMpMeVDDPDNφIn1In2In3Out1φMpMeVDDPDNφIn4φOut2MrVDDInputs = 0during prechargeCan be eliminated!2753Logical EffortLE =φOut54Delayed Precharge2855IBM’s 1GHz ProcessorSilberman et al, ISSCC’98JSSC 11/9856Domino PropertiesLogic evaluation propagates as falling dominoesEvaluation period determines the logic depthThe nodes must be precharged during the prechargeperiod (can limit the minimum size of PMOS)Inputs must be stable (or have only one rising transition) during the evaluationGates are ratiolessRestorer is ratioedAll the gates are non-invertingOnly one transition to be optimized2957Logic Design ProblemHow to design an XOR/MUX without a complementary signal available? We need it in datapaths!If the logic is followed by a flip-flop, or a latch with a hard edge, can use complementary or pass-transistor logicDomino logic is used with latches, and a new domino