1EE241 - Spring 2006Advanced Digital Integrated CircuitsLecture 16:Process Variations2Variability SourcesPhysicalChanges in characteristics of devices and wires.Caused by IC manufacturing process & wear-out (electro-migration).Time scale: 109sec (years).EnvironmentalChanges in VDD, Temperature, local coupling.Caused by the specifics of the design implementation.Time scale: 10−6to 10−9sec (clock tick).234Process VariationsControl of minimum features does not track feature scalingRelative device/interconnect variations increaseSources:Random dopant fluctuationsFeature size, oxide thickness variationsEffects:SpeedPower, primary leakageYield35Increasing Process VariationsIncrease in variation of process parameters with scalingWorst-case design getting more expensive“Better than worst-case” design must be error tolerantPercentage of total variation accounted for by within-die variation(device and interconnect)Original Source: Original Source: SaniSaniNassifNassifIBMIBM647020406080100120-39.71 -25.27 -10.83 3.61 18.0532.49ΔVTn(mv)# of Chips~30mVVt Distribution0.18 micron~1000 samplesLow FreqLow IsbHigh FreqMedium IsbHigh FreqHigh Isb8Sources of Variations101001000100001000 500 250 130 65 32Technology Node (nm)Mean Number of Dopant AtomsRandom Dopant Fluctuations0.010.111980 1990 2000 2010 2020micron101001000nm193nm193nm248nm248nm365nm365nmLithographyLithographyWavelengthWavelength65nm65nm90nm90nm130nm130nmGenerationGenerationGapGap45nm45nm32nm32nm13nm 13nm EUVEUV180nm180nmSource: Mark Bohr, IntelSub-wavelength Lithography5910Achieving Sub-wavelength Resolution611127131481516Causes Larger Frequency DistributionCourtesy IntelCourtesy Intel917Frequency & SD Leakage0.91.01.11.21.31.40 5 10 15 20Normalized Leakage (Isb)Normalized Frequency0.18 micron~1000 samples20X30%Low FreqLow IsbHigh FreqMedium IsbHigh FreqHigh Isb18Variation-tolerant Design00.511.5# uArch critical pathsless moreBalance power & frequency with variation tolerance00.511.5Logic depthsmalllargefrequencytarget frequency probability00.511.52Transistor sizesmalllargepowertarget frequency probability00.511.52Low-Vt usagelowhigh1019ApproachesWorst-case designLeaves too many crumbs on the table. Huge concurrency overhead for performance.Regular design strategies to reduce variationCareful choice of logic stylesSelf-adapting design.Turns on-line knobs (Vdd, Vt) to guarantee operation of the design. Uses one-time correction for systematic errorsAlternative Timing ApproachesSelf-timed or clockless designDefers the decisions to the system level. Comes with large overheadPseudo-synchronous design (e.g. Razor)Allows for occasional timing errors. Limited operation range.19 March 2006 Slide 20http://www.c2s2.orgwww.c2s2.orgProblem: Predictability ≈ (Chip Variability)-1Problem: Predictability ≈ (Chip Variability)-1Std library abstractions break:don’t “hide” the detailsanymore, as we scale downDefocuseffectDefocuseffectExposure variationResist effect(shrinks)(grows)Local printability problemsCu thickness distribCu thickness histogramGlobal effectsDemise of context-freelayout design rulesCorrelated randomvariations hit ckt level1119 March 2006 Slide 21http://www.c2s2.orgwww.c2s2.org“Fabrics” Idea: Atomic Regularity(Make the Variablility Small…Everywhere)“Fabrics” Idea: Atomic Regularity(Make the Variablility Small…Everywhere) Starting from basic manufacturingshapes Æcircuits Ælogic Ærouting everything is extremely regular Means radical re-architecting of flows How much predictability? At what cost? Initial motivation was “what’s after ASICs”, now more generally aimed at “predictability”Tomorrow’sdesignsToday’sdesignsRegular Geometry FabricRegular Geometry FabricRegular/Structured Integrated SystemRegular/Structured Integrated SystemRegular CircuitsRegular CircuitsASPDAC, Jan. 2005ASPDAC, Jan. 2005Regular Fabrics –A Plethora of ChoicesFPGAFPGAVPGACMUVPGACMURiver PLABerkeleyRiver PLABerkeleyStructured ASIC (e.g. LSI RapidChip)Structured ASIC (e.g. LSI RapidChip)Trade-off between area, performance, power and time-to-market (factors 5 to 10)TradeTrade--off between area, off between area, performance, power and performance, power and timetime--toto--market market (factors 5 to 10)(factors 5 to 10)1219 March 2006 Slide 23http://www.c2s2.orgwww.c2s2.orgFabric Architectures:Via Patterned Gate ArrayFabric Architectures:Via Patterned Gate Array Configurable with 4 masks for top vias Base architecture can be like an FPGA – but replace expensive switches with mask-config vias Many possible interconnect options: std cell routing, or fully regular top-level patterned routing Array offers fully predictable geom. patterning-2.9821960000Regular Logic VPGA flow-2.5211752048Standard ASIC flowSlack (ns)Area (um2)Network switch (80k Gates)VPGA regular logic +standard cell routing[Pileggi, CMU]19 March 2006 Slide 24http://www.c2s2.orgwww.c2s2.orgFabric Analysis: Enhanced Manufacturability for Regular Ckt FabricsFabric Analysis: Enhanced Manufacturability for Regular Ckt Fabrics Reduced CMP effects Copper dishing < 40Å Post-CMP Copper thickness variation is less than 2-3% Highly promising as a manufacturable ‘logic’replacement structureM4 Density of CMU VPGA FPUCu Dishing (M4) Final Post-CMP Cu Thickness (M4)Plated Thickness (M4) Oxide Erosion (M4)[Boning, MIT Pileggi, CMU]1319 March 2006 Slide 25http://www.c2s2.orgwww.c2s2.orgFabric-level Custom Circuit Design:Limited-Switch Dynamic Logic (LSDL)Fabric-level Custom Circuit Design:Limited-Switch Dynamic Logic (LSDL) Merges latch with every output stage Speed of domino – with less power Experiment: 16-bit Kogge-Stone adders, full domino vs LDSL 58 extracted 0.18um fab run models Monte-Carlo for chip-to-chip & mismatch LDSL: good for size & speed ~ 20% less area; ~2X faster  LSDL: good for regularity, var tolerance Cells more regular in content and size.  Less variation in pattern density. More tolerant of manufacturing variationLSDLDominoPolyM1Pattern DensityDomino LSDL [Montoye 03] Interchip+MismatchVariation[Boning, MIT]19 March 2006 Slide 26http://www.c2s2.orgwww.c2s2.orgFabric-Level Flow Design:“Regularizing” Cell-Based FlowsFabric-Level Flow Design:“Regularizing” Cell-Based FlowsComplementary approach:  Regularize a library-based flow Every cell is identical—except for vias Regularity issues handled by cell layout