EE241 Spring 2005 Advanced Digital Integrated Circuits Lecture 22 Adders Clock Generation Delay Locked Loop Delay Line Based fREF U Phase Det D Charge Pump DL Filter fO Phase Locked Loop VCO Based fREF U PD N D CP VCO Filter fO 2 1 Phase Locked Loop Based Clock Generator Up Down Reference clock Vcontr Up Loop filter Charge pump Phase detector VCO Down Local clock Clock decode buffer Divide by N 1 2 Acts also as Clock Multiplier 3 Loop Components Phase Comparator Produces UP DN pulses corresponding to phase difference Charge Pump Sources sinks current for duration of UP DN pulses Loop Filter Integrates current to produce control voltage Voltage Controlled Delay Line Changes delay proportionally to voltage Voltage Controlled Oscillator Generates frequency proportional to control voltage 4 2 PLL Jitter 5 DLL Locking Courtesy of IEEE Press New York 2000 6 3 Clock Deskewing Two clock spines two DLLs and a PD that controls them Geannopoulos ISSCC 98 7 Clock Ring Clocks routed in parallel opposite directions LCG aligns to the middle Shibayama ISSCC 98 8 4 Synchronous Distributed Oscillators VCOs of nearest neighbors Mizuno ISSCC 98 9 Distributed PLLs Gutnik ISSCC 2000 10 5 Intel ItaniumTM Rusu ISSCC 2000 11 Intel ItaniumTM 12 6 EE241 Spring 2005 Advanced Digital Integrated Circuits Arithmetic Arithmetic Circuits Chapter 11 Rabaey 2nd ed Selected journal publications Books K Hwang Computer Arithmetic Principles Architecture and Design John Wiley and Sons 1979 E E Swartzlander Computer Arithmetic Vol 1 2 IEEE Computer Society Press 1990 S Waser M Flynn Introduction to Arithmetic for Digital Systems Designers Holt Rinehart and Winston 1982 I Koren Computer Arithmetic Algorithms Brookside 1998 B Parhami Computer Arithmetic Oxford 2000 High Speed VLSI Arithmetic Units Adders and Multipliers by V Oklobdzija in Chandrakasan et al 14 7 Full Adder A Cin B Full adder Cout Sum 15 The Ripple Carry Adder A0 Ci 0 A1 B0 Co 0 FA FA A2 B1 A3 B2 Co 2 C o 1 FA FA S2 S3 B3 Co 3 Ci 1 S0 S1 Worst case delay linear with the number of bits td O N t adder N 1 tcarry tsum Goal Make the fastest possible carry path circuit 16 8 The Mirror Adder VDD VDD A B A VDD A B B Ci B Kill 0 Propagate A Ci Co Ci S Ci A 1 Propagate Generate A B A B B A Ci B Minimize inversions 17 Mirror Adder Cell VDD A B Ci B A Ci Co Ci A B Co S GND 18 9 Sizing Mirror Adder VDD VDD VDD A 12 B 12 B 4 0 Propagate A 4 B 4 Kill 12 A Ci 6 4 A 2 6B 2 Ci 4 Co 2 6 A 4 6 B 6 Ci 3 Ci 2 3 A 3 B S Generate 1 Propagate A 6 B A 2 B 2 Ci Fanout effective 2 19 Full Adder Implementation Standard CMOS Multiplexer based Courtesy of IEEE Press New York 2000 20 10 TG Based Full Adder P VDD V DD A Ci A P A B V DD A P B S Sum generation Ci P P V DD A Ci Ci P A Co Carry generation Ci P 21 Full Adder in DPL 22 11 Manchester Carry Chain Static Dynamic VDD VDD Pi Pi Gi Co Ci Co Ci Gi Ki Pi 23 Manchester Carry Chain Implement P with pass transistors Implement G with pull up kill delete with pull down Use dynamic logic to reduce the complexity and speed up VDD P0 P1 P2 P3 C3 Ci 0 G1 G0 G3 G2 C0 C1 Kilburn et al IEE Proc 1959 C2 C3 24 12 Sizing Manchester Carry Chain Discharge Transistor R1 1 MC C1 2 R2 M0 3 C2 R3 M1 R4 4 M2 C3 5 C4 R5 M3 6 C5 R6 M4 Out C6 N i tp 0 69 Ci R j i 1 j 1 25 400 20 300 Area Speed Tapering 15 100 10 5 1 200 1 5 2 0 2 5 3 0 k Speed normalized by 0 69RC 0 1 1 5 2 0 2 5 3 0 k Area in minimum size devices 25 Sizing Manchester Carry Chain Delay equation N i N N 1 t p 0 69 Ci R j 0 69 RC 2 i 1 j 1 Delay is quadratic with N Progressive sizing should help 26 13 Sizing Manchester Carry Chain Stick Diagram Propagate Generate Row VDD Pi Gi Pi 1 Gi 1 Cfix fixed capacitance Ci Ci 1 Ci 1 at the node pull down pull up diffusions metal inverter 15fF GND C 2fF m Inverter Sum Row R 10k m When CW Cfix N N 1 N N 1 R small improvements with C fix C W t p 0 69 RC 0 69 sizing 2 2 W Loading of the input stage 27 Manchester Carry Chain Length of chain is limited to k 4 8 Standard solution add inverters The overall N bit adder delay is a sum of N k segments linear 28 14 Carry Skip Adder G1 Ci 0 P0 G1 C o 0 P0 FA P2 FA G2 Co 1 FA G3 Co 3 FA G1 C o 0 P3 Co 2 FA P0 G1 G2 C o 1 FA Ci 0 P2 P3 G3 BP P oP1 P2 P3 C o 2 FA FA Multiplexer P0 Co 3 Idea If P0 and P1 and P2 and P3 1 then C o3 C 0 else kill or generate Bypass Skip MacSorley Proc IRE 1 61 Lehman Burla IRE Trans on Comp 12 61 29 Carry Skip Adder Bit 0 3 C i 0 Bit 4 7 Bit 8 11 Bit 12 15 Setup Setup Setup Setup Carry Propagation Carry Propagation Carry Propagation Carry Propagation Sum Sum Sum Sum Critical Path For N bit adder with k bit groups N td k 1 t RCA 2 t SKIP k 1 t RCA k 30 15 Carry Skip Adder Courtesy of IEEE Press New York 2000 31 Carry Skip Adder Critical path delay with constant groups N t d 2 k 1 t RCA 2 t SKIP k tp ripple adder bypass adder 4 8 N 32 16 Carry Skip Adder Variable Group Length t d c1 c2 N c3 Oklobdzija Barnes Arith 85 33 Carry Skip Adder Courtesy of IEEE Press New York 2000 34 17 Carry Skip Adder Variable Block Lengths Oklobdzija Barnes Arith 85 35 Manchester Chain with Carry Skip P0 P1 P2 P3 BP Co 3 Ci 0 G0 G1 G2 G3 BP Delay model 36 18 Carry Select Adder Setup P G 0 0 Carry Propagation 1 1 Carry Propagation Co k 1 Multiplexer Co k 3 Carry Vector Sum Generation 37 Carry Select Adder Critical Path Bit 0 3 Bit 4 7 Setup 0 0 Carry Setup 0 1 Carry 1 0 Carry 1 Carry 1 Multiplexer Ci 0 S0 3 Bit 12 15 Setup Setup 0 Carry Multiplexer S4 7 0 Carry 1 Carry 1 Multiplexer Co 7 Sum Generation 0 1 Carry 1 Co 3 Sum Generation 0 Bit 8 11 Multiplexer …