EE2411UC Berkeley EE241 B. NikolicEE241 - Spring 2002Advanced Digital Integrated CircuitsLecture 11Dynamic LogicUC Berkeley EE241 B. NikolicDynamic LogicMpMeVDDPDNφIn1In2In3OutMeMpVDDPUNφIn1In2In3φφOutCLCLφp networkφn network2 phase operation:• Evaluation • PrechargeEE2412UC Berkeley EE241 B. NikolicLogical EffortLE =φφInOutUC Berkeley EE241 B. NikolicLogical EffortLE =φφOutLE =φφOutEE2413UC Berkeley EE241 B. NikolicCascading Dynamic GatesMpMeVDDφφMpMeVDDφφInOut1Out2φOut2Out1InVt∆VVTn(a)(b)Only 0→1 Transitions allowed at inputs!UC Berkeley EE241 B. NikolicCascading Dynamic LogicEE2414UC Berkeley EE241 B. NikolicDomino LogicMpMeVDDPDNφIn1In2In3Out1φMpMeVDDPDNφIn4φOut2MrVDDStatic Inverterwith Level RestorerKrambeck et al, JSSC 6/82UC Berkeley EE241 B. NikolicLogical EffortLE =φφInOutInverter pair:Skewed inverter pair:EE2415UC Berkeley EE241 B. NikolicLogical effortLE =φφOutUC Berkeley EE241 B. NikolicDomino Logic - Characteristics• Only non-inverting logic• Very fast - Only 1->0 transitions at input of invertermove VM upwards by increasing PMOS• Adding level restorer reduces leakage andcharge redistribution problems• Optimize inverter for fan-outEE2416UC Berkeley EE241 B. NikolicDesigning with Domino LogicMpMeVDDPDNφIn1In2In3Out1φMpMeVDDPDNφIn4φOut2MrVDDInputs = 0during prechargeCan be eliminated!UC Berkeley EE241 B. NikolicLogical EffortLE =φOutEE2417UC Berkeley EE241 B. NikolicDelayed PrechargeUC Berkeley EE241 B. NikolicIBM’s 1GHz ProcessorSilberman et al, ISSCC’98JSSC 11/98EE2418UC Berkeley EE241 B. NikolicDomino Propertiesl Logic evaluation propagates as falling dominoesl Evaluation period determines the logic depthl The nodes must be precharged during the precharge period (can limit the minimum size of PMOS)l Inputs must be stable (or have only one rising transition) during the evaluationl Gates are ratiolessl Restorer is ratioedl All the gates are non-invertingl Only one transition to be optimizedUC Berkeley EE241 B. NikolicKey Problem in Dominol How to design an XOR/MUX without a complementary signal available?l We need it in datapathsl If the logic is followed by a flip-flop, or a latch with a hard edge, can use complementary or pass-transistor logicl Domino logic is used with latches, and a new domino stage may follow the XORl Solutions:» Use dual-rail domino (dynamic CVSL)» Violate some of domino rules (but still design a reliable circuit)» Force a hard edgeEE2419UC Berkeley EE241 B. NikolicSum Implementation (1)VDDClkGi64ClkSumVDDClkClkGi64ClkSi1ClkSi0KeeperUC Berkeley EE241 B. NikolicSum Implementation (2): Strobing[Park, VLSI’00]EE24110UC Berkeley EE241 B. NikolicMpMeVDDCLKCLKA B M1M2ABMpCLKO = ABO = ABVDDMf1Mf2Differential (Dual Rail) DominoDynamic CVSL (Clock CVSL) - Heller et al, ISSCC’84UC Berkeley EE241 B. NikolicDomino TechniquesConditional keeperStandard keeperConditional keeper[Alvandpour, VLSI’01]EE24111UC Berkeley EE241 B. NikolicStack Node PreconditioningDangerous: With stack nodepredischarged, charge sharingis a problem![Ye, VLSI’00]UC Berkeley EE241 B. NikolicClock-Delayed DominoEE24112UC Berkeley EE241 B. NikolicClock-Delayed DominoφDDVDφPossible implementation of delay blockNo need for inversionUC Berkeley EE241 B. NikolicNTP DominoNoise-tolerant precharge (NTP)Yamada, ICCD’95EE24113UC Berkeley EE241 B. NikolicOutput-Prediction LogicInverting logic:Output-prediction logic:McMurchie, et al, ICCD’2000UC Berkeley EE241 B. NikolicOutput-Prediction LogicNOR3:Clocking:McMurchie, et al, ICCD’2000EE24114UC Berkeley EE241 B. NikolicOutput-Prediction LogicNOR3 chain of 10:Clock separation:UC Berkeley EE241 B. NikolicMultiple-Output Domino (MODL)Hwang, Fisher, ISSCC’88F = F1F2Common subexpressionsEE24115UC Berkeley EE241 B. NikolicLookahead AdderMultiple Output Domino (MODL)GeneratePropagateUC Berkeley EE241 B. NikolicLookahead Adder4-bit group generate4-bit group propagateEE24116UC Berkeley EE241 B. NikolicCompound DominoHouston et al,U.S. Pat. 5,015,882May 1991.UC Berkeley EE241 B. Nikolicnp-CMOSMpMeVDDPDNφIn1In2In3φMeMpVDDPUNφIn4φOut1Out2Only 1→0 transitions allowed at inputs of PUNGoncavles, De Man JSSC 6/83Friedman, Liu, JSSC 4/84EE24117UC Berkeley EE241 B. Nikolicnp-CMOSOne-bit adderUC Berkeley EE241 B. NikolicNORA LogicMpMeVDDPDNIn1In2In3MeMpVDDPUNIn4Out1Out2To otherN-blocksTo other CLKCLKP-blocksCLKCLKEE24118UC Berkeley EE241 B. NikolicNORA LogicUC Berkeley EE241 B. NikolicClock and Data Precharged LogicDominoCDPDYuan, Svensson, Larson, Electronics Letters, 12/93EE24119UC Berkeley EE241 B. NikolicClock and Data Precharged