1EE241 - Spring 2006Advanced Digital Integrated CircuitsLecture 2:Scaling and ModelingDevice Models23Basic CMOS GateProperties• Output levels determined by supply• Large noise margins• Performance loss at low voltages (overdrives)VinVoutCLVDDVDDVDDVin5 VDDVin5 0VoutVoutRnRp4Digital GateBasic Properties• Functionality• Area (Cost)•Density• Robustness• Δ Swing, Noise margins, Noise sensitivity• Delay• tPLH, t PHL• Power, energy consumption35Transistor ModelsIn this class we will use a variety of transistor modelsAlways use the simplest one needed to analyze a particular effect6The MOS Transistor−GSDVGSVDS+Bp-substraten+n+V(x)xLIDMOS transistor with biasing47Transistor ModelingDifferent levels:Hand analysisComputer-aided analysis (e.g. Matlab)Switch-level simulation (e.g. TimeMill)Circuit simulation (Hspice)These levels have different requirements in complexity, accuracyand speed of computationWe are primarily interested in delay and energy modeling, ratherthan current modelingBut we have to start from the currents8MOS CurrentVertical field set by VGSinduces channel chargeGradual charge in the channel is assumedFixed charge in the channel is completely cancelled at VGS= VThCharge in the channel isQn= Cox(VGS– VTh- VC(x)) By Ohm’s law,IDS= WQn(x)v = WCox(VGS– VTh- VC(x)) μEAlso E = dVC(x)/dxKey assumption is that v = μE, and mobility (μ) is constant59MOS CurrentIDS= WCox(VGS– VTh- VC(x)) μEIDS= WCox(VGS– VTh- VC(x)) μ(VC(x)/dx)When integrated over the channel:DSDSThGSoxDSVVVVCLWI⎟⎠⎞⎜⎝⎛−−μ=2z Transistor saturates when VGD= VTh, - the channel pinches off at drain’s side.()22ThGSoxDSVVCLWI −μ=10MOS CurrentPinch-offSDVDS > VGS− VTVGSGVGS− VT−n+n++611MOS Currents020040060080010001200140016000 0.2 0.4 0.6 0.8 1 1.2VDS [V]IDS [μA]VGS = 1.2VVGS = 1.0VVGS = 0.8VVGS = 0.6VVGS = 0.4VCurrents according to the quadratic modelCorrect for long channel devices (L ~ μm)Quadratic12Simulated 0.13μm Transistor01002003004005006007000 0.2 0.4 0.6 0.8 1 1.2VDS [V]IDS [μA]0.4V0.6V0.8V1.0V1.2VL = 0.13μm600μA/μm~ Linear713Simulation vs. Model020040060080010001200140016000 0.2 0.4 0.6 0.8 1 1.2VDS [V]IDS [μA]Major discrepancies:• shape• saturation points• output resistancesModelDevice14Velocity SaturationE(V/µm)Ec= 1.5vn(m/s)vsat= 105Constant mobility (slope = µ)Constant velocity815Unified MOS Equations()()()⎪⎪⎪⎪⎩⎪⎪⎪⎪⎨⎧−>−>>⎟⎟⎠⎞⎜⎜⎝⎛−−′−<−>>−′−>−>>⎟⎟⎠⎞⎜⎜⎝⎛−−′<=THGSDSATTHGSDSTHGSDSATDSATTHGSTHGSDSATTHGSDSTHGSTHGSTHGSDSATTHGSDSTHGSDSDSTHGSTHGSDVVVVVVVVVVVVLWkVVVVVVVVVVLWkVVVVVVVVVVVVLWkVVI , ,,2 , ,,2 , ,,2,0222From EECS141Rabaey, 2nded.16MOS ModelsFrom EECS141Rabaey, 2nded.γ - body effect parameter917Unified MOS ModelModel presented is compact and suitable for hand analysis.Still have to keep in mind the main approximation: that VDSatis constant . When is it going to cause largest errors?When E scales – transistor stacks.But the model still works fairly well.18Velocity SaturationVelocity is not always proportional to fieldModeled through variable mobility (mobility degrades at high fields)nneffEEEv/101⎟⎟⎠⎞⎜⎜⎝⎛⎟⎟⎠⎞⎜⎜⎝⎛+μ=NMOS: n = 2PMOS: n = 1z Hard to solve for n =2z Assume n = 1 (close enough)effsatvEμ=20[Sodini84]1019Velocity SaturationWhen does a transistor enter velocity saturation?()()LEVVLEVVVCThGSCThGSDSat+−−=z ECis a function of vertical field, ~linearly proportional to VGS[Taur, Ning]20Velocity Saturation0.130.40.550.460.370.260VDSat[V]1.21.00.80.60.2VGS[V]z In 0.13μm technology, ECL is about 0.5VGS+ 0.7Vz Can calculate VDSat(VTh~ 0.25V)z For VGS–VTh<< ECL, (VGS< 1V)VDSatis close to VGS-VThz For large VGS, VDSatwould start bending upwards toward ECL, but we won’t even notice it with 1.2V supply.z Therefore ECL can be frequently approximated with a constant term (ECL= 1.2V in 0.13μm)1121Velocity Saturation01002003004005006007000 0.2 0.4 0.6 0.8 1 1.2VDS[V]IDS[V]0.4V0.6V0.8V1.0V1.2V22Drain CurrentWe can also find the current()()LEVVVVWCvICThGSThGSoxSatDSat+−−=2z Good model, could be used in hand or Matlab analysis()()LEVVVVLECLWICThGSThGSCoxeffDSat+−−μ=22()ThGSDSatoxeffDSatVVVCLWI −μ=21223Drain Current01002003004005006007000 0.2 0.4 0.6 0.8 1 1.2VDS[V]IDS[V]0.4V0.6V0.8V1.0V1.2Vsimulationunified modellinearsaturationvel. saturationVdsat24Output ResistanceSlope in I-V characteristics caused by:Channel length modulationDrain-induced barrier lowering (DIBL)Both effects increase the saturation current beyond the saturation pointThe simulations show approximately linear dependence of Idson Vdsin saturation.[BSIM 3v3 Manual]1325Output ResistanceChannel length modulationAs the drain voltage increases beyond the saturation voltage Vdsat, the saturation point moves slightly closer to the source (ΔL)The equation is modified by replacing L with ΔLTaylor expansion Ids= Idsat(1 + Vds/VA)ΔLSDVDSVGSGVdsat−n+n++26Output ResistanceDIBLIn a short channel device, source-drain distance is comparable to the depletion region widths, and the drain voltage can modulate the thresholdVTh= VTh- ξVdsTaylor expansionChannelL (D)0 (S)Long channelShort channelVds= 0.2V Vds= 1.2V[Taur, Ning]1427NAND GAte2-input NAND gateOutBVDDA2222Sizing for equal transistions:• P/N ratio (β-ratio) of 2 (more about this later in the class)• Upsizing stacks by a factor proportional to the stack height28Transistor StacksWith transistor stacks, VDS,VGSreduce.Unified model assumes VDSat= const.For a stack of two, appears that both have exactly double Rekvof an inverter with the same widthTherefore, doubling the size of each, should make the pull down R equivalent to an inverteroutV1529Velocity SaturationAs (VGS-VTh)/ECL changes, the depth of saturation changes()()LEVVVVLECLWICThGSThGSCoxeffDSat+−−μ=22z For VGS, VDS= 1.2V, ECL is 1.3V z With double length, ECL is 2.6V (in this model) z Stacked transistors are less saturatedz VGS-VTh= 0.95V, IDSat~ 2/3 of inverter IDSat(63%)z Therefore NAND2 should have pull down sized 1.5Xz Check any library NAND2’s30Velocity SaturationHow about NAND3?IDSat= 1/2 of inverter IDSat(instead of 1/3)How about PMOS networks?NOR2 – 1.8x, NOR3 – 2.4x, NOR4 - 3.2xWhat is ECL for PMOS?1631Alpha Power Law ModelAlternate approach, sometimes useful for hand analysis()α−μ=ThGSoxDSVVCLWI2z Parameter α is between 1 and 2.z In 0.13 - 0.25μm technology α ~ 1.2.[Sakurai, Newton, JSSC