EE2411UC Berkeley EE241 B. NikolicEE241 - Spring 2002Advanced Digital Integrated CircuitsLecture 27MemoryUC Berkeley EE241 B. NikolicReferencesl Rabaey, “Digital Integrated Circuits”l “Memory Design and Evolution,” VLSI Circuits Short Course, 1998.» Gillingham, Evolution of DRAM» Nuhn, Cao, MacGillivray, DRAM Development Trendsl Chapter 14, Register Files and Caches, by R. Prestonl Chapter 15, Embedded DRAM, by Yamauchi and YamadaEE2412UC Berkeley EE241 B. NikolicSemiconductor Memory ClassificationRWMNVRWM ROMEPROME2PROMFLASHRandomAccessNon-RandomAccessSRAM DRAMMask-ProgrammedProgrammable (PROM)FIFOShift RegisterCAMLIFOUC Berkeley EE241 B. NikolicArray-Structured Memory ArchitectureInput-Output(M bits)Row DecoderAKAK+1AL-12L-KColumn DecoderBit LineWord LineA0AK-1Storage CellSense Amplifiers / DriversM.2KProblem: ASPECT RATIO or HEIGHT >> WIDTHAmplify swing torail-to-rail amplitudeSelects appropriatewordEE2413UC Berkeley EE241 B. NikolicMemory CellsUC Berkeley EE241 B. NikolicRead-Write Memories (RAM)• STATIC (SRAM)• DYNAMIC (DRAM)Data stored as long as supply is appliedLarge (6 transistors/cell)FastDifferentialPeriodic refresh requiredSmall (1-3 transistors/cell)SlowerSingle EndedEE2414UC Berkeley EE241 B. Nikolic3-Transistor DRAM CellM2M1BL1WWLBL2M3RWLCSXWWLRWLXBL1BL2VDD-VT∆VVDDVDD-VTNo constraints on device ratiosReads are non-destructiveValue stored at node X when writing a “1” = VWWL-VTnUC Berkeley EE241 B. Nikolic1-Transistor DRAM CellCSM1BLWLCBLWLXBLVDD−VTVDD/2VDDGNDWrite "1"Read "1"sensingVDD/2∆VVBLVPRE– VBITVPRE–()CSCSCBL+------------------------= =Write: CS is charged or discharged by asserting WL and BL.Read: Charge redistribution takes places between bit line and storage capacitanceVoltage swing is small; typically around 250 mV.EE2415UC Berkeley EE241 B. NikolicDRAM1T DRAM requires a sense amplifier for each bit line, due to charge redistribution read-out.DRAM memory cells are single ended in contrast to SRAM cells.The read-out of the 1T DRAM cell is destructive; read and refresh operations are necessary for correct operation.Unlike 3T cell, 1T cell requires presence of an extra capacitance that must be explicitly included in the design.When writing a “1” into a DRAM cell, a threshold voltage is lost. This charge loss can be circumvented by bootstrapping the word lines to a higher value than VDD.UC Berkeley EE241 B. Nikolic1-T DRAM Cell(a) Cross-section(b) LayoutDiffusedbit linePolysiliconplateM1 wordlineCapacitorPolysilicongateMetal word lineSiO2n+Field OxideInversion layerinduced by plate biasn+polypolyUsed Polysilicon-Diffusion CapacitanceExpensive in AreaEE2416UC Berkeley EE241 B. NikolicAdvanced 1T DRAM CellsCell Plate SiCapacitor InsulatorStorage Node Poly2nd Field OxideRefilling PolySi SubstrateTrench CellStacked-capacitor CellInsulating LayerIsolationTransfer gateStorage electrodeUC Berkeley EE241 B. NikolicDRAM Evolutionl “Memory Design and Evolution,” VLSI Circuits Short Course, 1998.» Gillingham, Evolution of DRAM» Nuhn, Cao, MacGillivray, DRAM Development TrendsEE2417UC Berkeley EE241 B. Nikolic1K DRAMl Intel 1103, late 1971.l Cost effective - <1c/bitl PMOS, silicon gate, 1M1Pl Vdd=0V, Vss=16V, Vbb=20Vl 300ns access, 580ns cycle, 2ms retentionUC Berkeley EE241 B. Nikolic4k DRAMl Texas Instruments TMS4030, introduced 1973l NMOS 1M1P, TTL I/Ol 1T Cell, Differential Sense Ampl Vdd=12V, Vcc=5V, Vbb=-5V, Vss=0VEE2418UC Berkeley EE241 B. Nikolic16k DRAMl MOSTEK MK4116, introduced 1977l Address multiplexl NMOS 2P1Ml Vdd=12V, Vcc=5V, Vbb=-5V, Vss=0VUC Berkeley EE241 B. Nikolic64K DRAMl 1980, NMOS 2P1Ml 5V only, internal Vbb generatorl Boosted wordline, eliminate Vt lossEE2419UC Berkeley EE241 B. Nikolic256K DRAMl Folded bitline architecturel NMOS 2P1M, poly 2 (polycide), gate, W/L, 5Vl Redundancyl Active restoreUC Berkeley EE241 B. Nikolic1M DRAMl CMOS, N-well, Vbb substrate, 3P1Ml Boosted circuitsl Vdd/2 bitline reference, Vdd/2 cell plateEE24110UC Berkeley EE241 B. Nikolic4M DRAMl CMOS 4P1Ml x16 output, self refreshl 3D cell structures, stacked or trenchUC Berkeley EE241 B. Nikolic16M DRAMl CMOS 4p2M, Vdd=5V, internally 3-4Vl EDO – Extended Data OutEE24111UC Berkeley EE241 B. NikolicRow DecodersCollection of 2Mcomplex logic gatesOrganized in regular and dense fashion(N)AND DecoderNOR DecoderUC Berkeley EE241 B. NikolicA NAND decoder using 2-input pre-decodersA0A1A0A1A0A1A0A1A2A3A2A3A2A3A2A3A1A0A0A1A3A2A2A3WL0WL1Splitting decoder into two or more logic layersproduces a faster and cheaper implementationEE24112UC Berkeley EE241 B. NikolicDecodersl Word line selection results in only one critical transitionl Skew the gates sizingl Requires resetting for the next transitionl Prechargingl Self-resetting; Delayed-resettingUC Berkeley EE241 B. NikolicDynamic DecodersWL3GNDGNDPrecharge devicesWL2WL1WL0VDDφA0A0A1A1A0A0A1A1VDDVDDVDDVDDφWL3WL2WL1WL0Dynamic 2-to-4 NOR decoder 2-to-4 MOS dynamic NAND DecoderPropagation delay is primary concernEE24113UC Berkeley EE241 B. NikolicPrecharged Decodersl Most designs use NAND-based designl NOR based design has a speed advantage, but big power problem» All outputs are initially precharged» When decoder evaluates, 2M-1outputs discharge, only one stays high – power probleml In NAND-based designs only one output changesl Clock power is still very large: precharge and evaluate transistors switch every cycleUC Berkeley EE241 B. NikolicSelf-Resetting DecodersChappell, JSSC 11/91EE24114UC Berkeley EE241 B. NikolicSelf-Resetting DecodersPark, ISSCC’984Mb DDR SRAMUC Berkeley EE241 B. NikolicSource-Coupled LogicStatic DynamicSource-CoupledNambu, JSSC 11/98EE24115UC Berkeley EE241 B. NikolicSource-Coupled LogicConventional Decoder Source-CoupledUC Berkeley EE241 B. NikolicSense AmplifierstpC∆V⋅Iav----------------=make ∆V as smallas possiblesmalllargeIdea: Use Sense Ampliferoutputinputs.a.smalltransitionEE24116UC Berkeley EE241 B. NikolicDifferential Sensing - SRAMDiff.SenseAmpBLBLSRAM cell ix xyyD DVDDVDDWLiPCEQVDDx xySEVDDxxySEVDDx xySE(b) Doubled-ended Current Mirror Amplifiery(a) SRAM sensing scheme.(c) Cross-Coupled AmplifierM1 M2M4M3M5UC Berkeley EE241 B. NikolicLatch-Based Sense AmplifierVDDBLSESEBLEQInitialized in its meta-stable point with EQOnce adequate voltage gap created, sense amp enabled with SEPositive feedback quickly forces output to a stable operating point.EE24117UC Berkeley EE241 B. NikolicOpen Bitline