EE2411UC Berkeley EE241 B. NikolicEE241 - Spring 2000Advanced Digital Integrated CircuitsLecture 3Circuit Optimization for SpeedUC Berkeley EE241 B. NikolicAnnouncementsl Tu 2/8/00 class will be pre-taped on Friday, 2/4, 4-5:30 203 McLaughlinl Class notes are available in the morning before the class on the Webl ISSCC preview seminars:» Fri 1/28, 2-5pm, 531 Cory (Hogan Rm) - 5 speakers from Stanford» Tue 2/1 3:30-5:30pm, 531 Cory – 4 speakers from Philips» Thu 2/3 4-5 531 Cory – 2 speakers from UC DavisEE2412UC Berkeley EE241 B. NikolicStatic CMOS Delayl Intrinsic logic delay» From internal R, C = constantl RC delay of the load» Fan-out» Wire RCl For a given gate, delay is a function of:» Load» Input rise time(s)» Intrinsic delayUC Berkeley EE241 B. NikolicDelay model application:intrinsic delayClose to Shoji2CD+CGEE2413UC Berkeley EE241 B. NikolicDelay dependence on inputs-1.00.01.02.03.0VDDCLFRPRPRNRNAABBCinttime, psA = 1→0, B =1A = B = 1→0A = 1, B = 1→0 0 100 200 300 400UC Berkeley EE241 B. NikolicOptimizing the intrinsic RC delayEE2414UC Berkeley EE241 B. NikolicProgressive SizingUC Berkeley EE241 B. NikolicUniform versus progressive sizingUniformkn-1kn-1NNon-uniform1kk2kn-1EE2415UC Berkeley EE241 B. NikolicSizing modelsUC Berkeley EE241 B. NikolicCase studyEE2416UC Berkeley EE241 B. NikolicExample: Progressive Scaling of NMOS Devices in DOMINO CMOSUC Berkeley EE241 B. NikolicWhat if External Capacitance is Dominant?Divide and Conquer!EE2417UC Berkeley EE241 B. NikolicDivide and ConquerC2C1CiCL1uu2uN-1In Outuopt = eUC Berkeley EE241 B. Nikolictpas a function of u and x1.0 3.0 5.0 7.0u0.020.040.060.0u/ln(u)x=10x=100x=1000x=10,000EE2418UC Berkeley EE241 B. NikolicAdding Intrinsic LoadUC Berkeley EE241 B. NikolicOptimum Tapering Factor for Realistic Load0 1 2 3α = gγ 2345uoptEE2419UC Berkeley EE241 B. NikolicTapering Factor for Realistic LoadUC Berkeley EE241 B. NikolicEffect of Rise/Fall TimesEE24110UC Berkeley EE241 B. NikolicEffect of Rise/Fall TimesUC Berkeley EE241 B. NikolicNegative Delay?EE24111UC Berkeley EE241 B. NikolicImpact of Rise and Fall TimesUC Berkeley EE241 B. NikolicImpact of Terminationkoko k1fNmCLEE24112UC Berkeley EE241 B. NikolicRequired Number of Buffer StagesUC Berkeley EE241 B. NikolicWhat about power consumption (and area)?EE24113UC Berkeley EE241 B. NikolicDelay versus Area and PowerUC Berkeley EE241 B. NikolicOptimizing tpversus tr/tfEE24114UC Berkeley EE241 B. NikolicProblem: Ground BounceUC Berkeley EE241 B. NikolicSizing in Presence of NoiseEE24115UC Berkeley EE241 B. NikolicRC-line delayWaveforms for 10 mm RC Line: tp = 750 psec0.35 µm processminimum width wiresr = 0.12 Ω/µmc = 0.16 fF/µmτ = 0.019 fs/µm2O mm1O mmUC Berkeley EE241 B. NikolicDelay and Rise Times for a 10 mm lineSimulation ResultsAnalytically:td= 0.4 d2RCtr= d2RCEE24116UC Berkeley EE241 B. NikolicRepeatersOptimum repetition ratetd= (l/ls)2tbFor 0.35 µm tech.ls= 3.5 mmν = 17.5 mm/nsUC Berkeley EE241 B. NikolicIncreasing Wire Width and SpacingReduces impact of fringing capacitance and capacitance to neighboring wiresEE24117UC Berkeley EE241 B. NikolicOverdrive of Low-Swing RC Lines300 mV signal1.5 V overdrive750 ps -> 350 psUC Berkeley EE241 B. NikolicBipolar Overdrive SignalingIssues:• Crosstalk• Delay still quadratic with respect to lengthEE24118UC Berkeley EE241 B. NikolicImpact of wire-delay on high-performance design1 2Ntd stageLnettd global= td inv+ td EdgeLEdgeGlobal Wiretd cycle= N∗ td stage+ td globaltd= Ro(Cout+ f.o.Cg in) + Ro(Cw) + 0.4(CwRw1.6+ tof1.6)1/1.6 + 0.7RwCg inCritical Path Delay Model (Phil Fischer - Sematech)UC Berkeley EE241 B. NikolicTransistor and Interconnect ParametersParameter250nm180nm150nm130nm100nm70nm50nmWint M1-2 local (nm) 320 230 195 170 130 95 70Hint M1-2 local (nm) 576 420 390 360 312 257 210Pitchw M1-2 local (nm) 640 460 390 340 260 190 140tins M1-2 local (nm) 650 500 450 360 320 270 210Wint M semi-global (nm) 500Hint M semi-global (nm) 900Pitchw M semi-global (nm)15001000900800600400350tins M semi-global (nm)900Wint M global (nm)2000Hint M global (nm)2000Pitchw M global(nm) 4000 4000 4000 4000 4000 4000 4000tins M global (nm) 1400Chip area (cm2)3.03.63.94.35.26.27.5Vdd (V)2.51.81.81.51.20.90.6Metal Levels 6 6 6 7 8 9 9Metal resistivity (µohm-cm)3.32.22.22.22.21.81.8Relative dielectric constant 3.9 2.7 2.5 2.0 1.5 1.4 1.4Transistors:Equivalent tox (nm) 4.50 3.50 2.80 2.50 1.80 1.40 1.00In nominal (µa/µm)600600600600600600600Ip nominal (µa/µm)280280280280280280280EE24119UC Berkeley EE241 B. NikolicNAND Gate Stage Delay (with scaled local interconnect, fi = fo = 3)0204060801001201404090140190240Technology Min. Feature (nm)Delay (ps)Gate delayWire delayStage delay250 180 150 100 70 50130For future Cu-low κSource: P. FischerUC Berkeley EE241 B. NikolicHigh-Performance Microprocessor04008001200160020002400280032004090140190240Technology Min. Feature (nm)Clock Freq. (MHz)250 180 130 100 70 50Logic Depth = 12 Gates150Cu-Low κ Al -Low κAl -SiO2Cu-SiO2EE24120UC Berkeley EE241 B. NikolicClock-Cycle Model SummaryLnet Logic wire CP (µm) 175 139 126 103 78 59 48Cint M1 (pF/cm) 1.92 1.21 1.16 0.97 0.77 0.76 0.81Cint 2µm M global (pF/cm) 1.86 1.29 1.19 0.95 0.72 0.67 0.67Rint M1 (Kohm/cm)1.82.52.93.65.47.412.3Rint 2µm M global (ohm/cm)83555555554545tof (ps/cm) 80 64 57 57 49 48 48Ledge (cm) 1.73 1.90 1.96 2.07 2.28 2.49 2.74td-global (ps) 377 235 210 190 176 168 160td-gates Logic D=12 (ps) 830 512 428 370 274 193 139td-cycle Model (ps) 1207 746 637 560 450 361 299tcycle time (ps) 1341 829 708 622 500 401 332Ratio (td-cycle/tcycle time) 0.90 0.90 0.90 0.90 0.90 0.90 0.90High Perf. Clock, µP (MHz)746120614121607200124973015 Rounded Clock, µP (MHz)750120014001600200025003000 Cost - Performance (D=25)Cost Perf. Clock, µP (MHz)380615727833107214061782 Rounded Clock, µP (MHz)400600700800110014001800Wn Output (µm) 6.0 4.0 3.5 3.0 2.0 1.5 1.0Logic Area (cm2) 1.20 1.15 1.18 1.10 1.11 1.11 1.10Ng 1.00E+06 1.50E+06 2.00E+06 3.00E+06 6.00E+06 1.20E+07 2.00E+07Ntr Logic 6.00E+06 9.00E+06 1.20E+07 1.80E+07 3.60E+07 7.20E+07 1.20E+08Parameter 250nm 180nm 150nm 130nm 100nm 70nm 50nmUC Berkeley EE241 B. NikolicRules of Thumbl Keep the fan-in less than 3l Keep the fan-out less than 5l Same delays of gates in the critical pathl Same rise/fall times l Size the transistors to drive the interconnectEE24121UC Berkeley EE241 B. NikolicLogical Effort“Designing for speed on the Back of an