New version page

UMD ENEE 759H - TOSHIBA MOS DIGITAL INTEGRATED CIRCUIT

This preview shows page 1-2-3-4-25-26-27-52-53-54-55 out of 55 pages.

View Full Document
View Full Document

End of preview. Want to read all 55 pages?

Upload your study docs or become a GradeBuddy member to access this document.

View Full Document
Unformatted text preview:

TC59LM818DMBI-40 2003-02-28 1/55 TENTATIVE TOSHIBA MOS DIGITAL INTEGRATED CIRCUIT SILICON MONOLITHIC 4,194,304-WORDS × 4 BANKS × 18-BITS Network FCRAMTM DESCRIPTION Network FCRAMTM is Double Data Rate Fast Cycle Random Access Memory. TC59LM818DMBI is Network FCRAMTM containing 301,989,888 memory cells. TC59LM818DMBI is organized as 4,194,304-words × 4 banks × 18 bits. TC59LM818DMBI feature a fully synchronous operation referenced to clock edge whereby all operations are synchronized at a clock input which enables high performance and simple user interface coexistence. TC59LM818DMBI can operate fast core cycle compared with regular DDR SDRAM. TC59LM818DMBI is suitable for Network, Server and other applications where large memory density and low power consumption are required. The Output Driver for Network FCRAMTM is capable of high quality fast data transfer under light loading condition. TC59LM818DMBI guarantees −40deg°C to 100deg°C operating temperature so it is suitable for use in wide operating temperature system. FEATURES+ TC59LM818DMBI PARAMETER -40 CL = 4 5.0 ns CL = 5 4.5 ns tCK Clock Cycle Time (min) CL = 6 4.0 ns tRC Random Read/Write Cycle Time (min) 25 ns tRAC Random Access Time (max) 25 ns IDD1S Operating Current (single bank) (max) 210 mA lDD2P Power Down Current (max) 50 mA lDD6 Self-Refresh Current (max) 10 mA • Fully Synchronous Operation • Double Data Rate (DDR) Data input/output are synchronized with both edges of DS / QS. • Differential Clock (CLK and CLK ) inputs CS , FN and all address input signals are sampled on the positive edge of CLK. Output data (DQs and QS) is aligned to the crossings of CLK and CLK . • Fast clock cycle time of 4.0 ns minimum Clock: 250 MHz maximum Data: 500 Mbps/pin maximum • Operating Temperature : −40deg°C ~ 100deg°C (Case Temperature) • Quad Independent Banks operation • Fast cycle and Short Latency • Selectable Data Strobe • Distributed Auto-Refresh cycle in 1.0 µs • Self-Refresh • Power Down Mode • Variable Write Length Control • Write Latency = CAS Latency-1 • Programable CAS Latency and Burst Length CAS Latency = 4, 5, 6 Burst Length = 2, 4 • Organization: 4,194,304 words × 4 banks × 18 bits • Power Supply Voltage VDD: 2.5 V ± 0.125V VDDQ: 1.4 V ~ 1.9 V • Low voltage CMOS I/O covered with SSTL-18 (Half strength driver) and HSTL • Package: 60Ball BGA, 1mm × 1mm Ball pitch (P-BGA60-0917-1.00AZ) Notice: FCRAM is trademark of Fujitsu limited, Japan.TC59LM818DMBI-40 2003-02-28 2/55 PIN NAMES PIN ASSIGNMENT (TOP VIEW) PIN NAME A0~A14 Address Input BA0, BA1 Bank Address DQ0~DQ17 Data Input/Output CS Chip Select FN Function Control PD Power Down Control CLK, CLK Clock Input DS / QS Write/Read Data Strobe VDD Power (+2.5 V) VSS Ground VDDQ Power (+1.5 V, +1.8 V) (for DQ buffer) VSSQ Ground (for DQ buffer) VREF Reference Voltage NC Not Connected 5 ABCDEFGHJK1 3 6 4 2x18IndexLMNPRVSSDQ17 DQ0 VDDDQ16 VSSQ VDDQ DQ1DQ15 VDDQ VSSQ DQ2DQ14 DQ13 DQ4 DQ3DQ12 VSSQ VDDQ DQ5DQ11 VDDQ VSSQ DQ6DQ10 VSSQ VDDQ DQ7DQ9 DS QS DQ8VREF VSSVDD A14CLKCLK FN A13NCA12PDCSBA0A11 A9 BA1 A10A8 A7 A0 A1A5 A6 A2 VDDVSSA4 A3 ball pitch=1.0 x 1.0mm : Depopulated BallTC59LM818DMBI-40 2003-02-28 3/55 BLOCK DIAGRAM Note: The TC59LM818DMBI configuration is 4 Bank of 32768 × 128 × 18 of cell array with the DQ pins numbered DQ0~DQ17. DQ0~DQ17 BANK #1 DLL CLOCK BUFFER CLK CLK PDTo each blockCOMMAND DECODER CSFN ADDRESS BUFFER CONTROL SIGNAL GENERATOR MODE REGISTER REFRESH COUNTER A0~A14BA0, BA1BANK #0 MEMORY CELL ARRAY COLUMN DECODERROW DECODER BURST COUNTER WRITE ADDRESS LATCH/ ADDRESS COMPARATOR DATA CONTROL and LATCH CIRCUIT UPPER ADDRESS LATCH READ DATA BUFFER DQ BUFFER DSLOWER ADDRESS LATCH BANK #2 BANK #3 WRITE DATA BUFFERQSTC59LM818DMBI-40 2003-02-28 4/55 ABSOLUTE MAXIMUM RATINGS SYMBOL PARAMETER RATING UNIT NOTES VDD Power Supply Voltage −0.3~ 3.3 V VDDQ Power Supply Voltage (for DQ buffer) −0.3~VDD+ 0.3 V VIN Input Voltage −0.3~VDD+ 0.3 V VOUT Output and I/O pin Voltage −0.3~VDDQ + 0.3 V VREF Input Reference Voltage −0.3~VDD+ 0.3 V Topr Operating Temperature (Ambient) −40~85 °C Tstg Storage Temperature −55~150 °C Tsolder Soldering Temperature (10 s) 260 °C PD Power Dissipation 2 W IOUT Short Circuit Output Current ±50 mA Caution: Conditions outside the limits listed under “ABSOLUTE MAXIMUM RATINGS” may cause permanent damage to the device. The device is not meant to be operated under conditions outside the limits described in the operational section of this specification. Exposure to “ABSOLUTE MAXIMUM RATINGS” conditions for extended periods may affect device reliability. RECOMMENDED DC, AC OPERATING CONDITIONS (Notes: 1)(TCASE = -40~100°C) SYMBOL PARAMETER MIN TYP. MAX UNIT NOTESVDD Power Supply Voltage 2.375 2.5 2.625 V VDDQ Power Supply Voltage (for DQ buffer) 1.4  1.9 V VREF Reference Voltage VDDQ/2 × 95% VDDQ/2 VDDQ/2 × 105% V 2 VIH (DC) Input DC High Voltage VREF + 0.125  VDDQ + 0.2 V 5 VIL (DC) Input DC Low Voltage −0.1  VREF − 0.125 V 5 VICK (DC) Differential Clock DC Input Voltage −0.1  VDDQ + 0.1 V 10 VID (DC) Differential Input Voltage CLK and CLK inputs (DC) 0.4  VDDQ + 0.2 V 7, 10VIH (AC) Input AC High Voltage VREF + 0.2  VDDQ + 0.2 V 3, 6 VIL (AC) Input AC Low Voltage −0.1  VREF − 0.2 V 4, 6 VID (AC) Differential Input Voltage. CLK and CLK inputs (AC) 0.55  VDDQ + 0.2 V 7, 10VX (AC) Differential AC Input Cross Point Voltage VDDQ/2 − 0.125  VDDQ/2 + 0.125 V 8, 10VISO (AC) Differential Clock AC Middle Level VDDQ/2 − 0.125  VDDQ/2 + 0.125 V 9, 10TC59LM818DMBI-40 2003-02-28 5/55 Note: (1) All voltages referenced to VSS, VSSQ. (2) VREF is expected to track variations in VDDQ DC level of the transmitting device. Peak to peak AC noise on VREF may not exceed ±2% VREF (DC). (3) Overshoot limit: VIH (max) = VDDQ + 0.7 V with a pulse width ≤ 5 ns. (4) Undershoot limit: VIL (min) = −0.7 V with a pulse width ≤ 5 ns. (5) VIH (DC) and VIL (DC) are levels to maintain the current logic state. (6) VIH (AC) and VIL (AC) are levels to change to the new logic state. (7) VID is differential voltage of CLK input level and CLK input level. (8) The value of VX (AC) is expected to equal VDDQ/2 of the transmitting device. (9) VISO means {VICK (CLK) + VICK (CLK )} /2


View Full Document
Loading Unlocking...
Login

Join to view TOSHIBA MOS DIGITAL INTEGRATED CIRCUIT and access 3M+ class-specific study document.

or
We will never post anything without your permission.
Don't have an account?
Sign Up

Join to view TOSHIBA MOS DIGITAL INTEGRATED CIRCUIT and access 3M+ class-specific study document.

or

By creating an account you agree to our Privacy Policy and Terms Of Use

Already a member?