HIGH-SPEEDMEMORY SYSTEMS Spring 2003Bruce Jacob David WangUniversity of Maryland Lecture 11 Page 1 Basics DRAM ORGANIZATION... Bit Lines...MemoryArrayRow Decoder. .. Word Lines ...DRAMStorage elementSwitching elementBit LineWord LineData In/OutBuffersSense AmpsColumn Decoder(capacitor)HIGH-SPEEDMEMORY SYSTEMS Spring 2003Bruce Jacob David WangUniversity of Maryland Lecture 11 Page 2 Basics BUS TRANSMISSIONBUSMEMORYCONTROLLERCPU... Bit Lines...MemoryArrayRow Decoder. .. Word Lines ...DRAMData In/OutBuffersSense AmpsColumn DecoderHIGH-SPEEDMEMORY SYSTEMS Spring 2003Bruce Jacob David WangUniversity of Maryland Lecture 11 Page 3 Basics [PRECHARGE and] ROW ACCESS AKA: OPEN a DRAM Page/RowRAS (Row Address Strobe)ororACT (Activate a DRAM Page/Row)BUSMEMORYCONTROLLERCPU... Bit Lines...MemoryArrayRow Decoder. .. Word Lines ...DRAMData In/OutBuffersSense AmpsColumn DecoderHIGH-SPEEDMEMORY SYSTEMS Spring 2003Bruce Jacob David WangUniversity of Maryland Lecture 11 Page 4 Basics COLUMN ACCESS READ CommandorCAS: Column Address StrobeBUSMEMORYCONTROLLERCPU... Bit Lines...MemoryArrayRow Decoder. .. Word Lines ...DRAMData In/OutBuffersSense AmpsColumn DecoderHIGH-SPEEDMEMORY SYSTEMS Spring 2003Bruce Jacob David WangUniversity of Maryland Lecture 11 Page 5 Basics DATA TRANSFER note: page mode enables overlap with CASBUSMEMORYCONTROLLERCPU... Bit Lines...MemoryArrayRow Decoder. .. Word Lines ...DRAMData In/OutBuffersSense AmpsColumn Decoder... with optional additionalCAS: Column Address StrobeData OutHIGH-SPEEDMEMORY SYSTEMS Spring 2003Bruce Jacob David WangUniversity of Maryland Lecture 11 Page 6 Basics BUS TRANSMISSIONBUSMEMORYCONTROLLERCPU... Bit Lines...MemoryArrayRow Decoder. .. Word Lines ...DRAMData In/OutBuffersSense AmpsColumn DecoderHIGH-SPEEDMEMORY SYSTEMS Spring 2003Bruce Jacob David WangUniversity of Maryland Lecture 11 Page 7 Basics BCDDRAME2/E3E1FACPUMemControllerA: Transaction request may be delayed in QueueB: Transaction request sent to Memory ControllerC: Transaction converted to Command Sequences(may be queued)D: Command/s Sent to DRAME1: Requires only a CAS orE2: Requires RAS + CAS orF: Transaction sent back to CPU“DRAM Latency” = A + B + C + D + E + FE3: Requires PRE + RAS + CASHIGH-SPEEDMEMORY SYSTEMS Spring 2003Bruce Jacob David WangUniversity of Maryland Lecture 11 Page 8 Basics Read Timing for Conventional DRAMRowAddressColumnAddressValidDataoutRASCASAddressDQRowAddressColumnAddressValidDataoutData TransferColumn AccessRow AccessHIGH-SPEEDMEMORY SYSTEMS Spring 2003Bruce Jacob David WangUniversity of Maryland Lecture 11 Page 9 DRAM Evolutionary Tree(Mostly) Structural ModificationsInterface ModificationsStructuralConventionalFPM EDOESDRAMRambus, DDR/2 Future Trends. . . . . . . . . . . . . . MOSYSFCRAMVCDRAM$ModificationsTargetingLatencyTargeting ThroughputTargeting ThroughputDRAMSDRAMP/BEDOHIGH-SPEEDMEMORY SYSTEMS Spring 2003Bruce Jacob David WangUniversity of Maryland Lecture 11 Page 10 DRAM Evolution Read Timing for Conventional DRAMRowAddressColumnAddressValidDataoutRASCASAddressDQRowAddressColumnAddressValidDataoutData TransferColumn AccessTransfer OverlapRow AccessHIGH-SPEEDMEMORY SYSTEMS Spring 2003Bruce Jacob David WangUniversity of Maryland Lecture 11 Page 11 DRAM Evolution Read Timing for Fast Page ModeRowAddressColumnAddressValidDataoutColumnAddressColumnAddressValidDataoutValidDataoutRASCASAddressDQData TransferColumn AccessTransfer OverlapRow AccessHIGH-SPEEDMEMORY SYSTEMS Spring 2003Bruce Jacob David WangUniversity of Maryland Lecture 11 Page 12DRAM EvolutionRead Timing for Extended Data OutRowAddressColumnAddressValidDataoutRASCASAddressDQColumnAddressColumnAddressValidDataoutValidDataoutData TransferColumn AccessTransfer OverlapRow AccessHIGH-SPEEDMEMORYSYSTEMSSpring 2003Bruce JacobDavid WangUniversity ofMarylandLecture 11Page 13DRAM EvolutionRead Timing for Burst EDORowAddressColumnAddressRASCASAddressDQData TransferColumn AccessTransfer OverlapRow AccessValidDataValidDataValidDataValidDataHIGH-SPEEDMEMORYSYSTEMSSpring 2003Bruce JacobDavid WangUniversity ofMarylandLecture 11Page 14DRAM EvolutionRead Timing for Pipeline Burst EDORowAddressColumnAddressRASCASAddressDQData TransferColumn AccessTransfer OverlapRow AccessValidDataValidDataValidDataValidDataHIGH-SPEEDMEMORYSYSTEMSSpring 2003Bruce JacobDavid WangUniversity ofMarylandLecture 11Page 15DRAM EvolutionRead Timing for Synchronous DRAM(RAS + CAS + OE ... == Command Bus)CommandAddressDQClockRowAddrColAddrValidDataValidDataValidDataValidDataACTREADRASCASData TransferColumn AccessTransfer OverlapRow AccessHIGH-SPEEDMEMORYSYSTEMSSpring 2003Bruce JacobDavid WangUniversity ofMarylandLecture 11Page 16DRAM EvolutionInter-Row Read Timing for ESDRAMCommandAddressDQClockRowAddrColAddrValidDataValidDataValidDataValidDataACTREADRowAddrColAddrValidDataValidDataValidDataValidDataACTREADPRERegular CAS-2 SDRAM, R/R to same bankCommandAddressDQClockRowAddrColAddrValidDataValidDataValidDataValidDataACT READRowAddrColAddrValidDataValidDataValidDataValidDataACT READESDRAM, R/R to same bankPREBankBankHIGH-SPEEDMEMORYSYSTEMSSpring 2003Bruce JacobDavid WangUniversity ofMarylandLecture 11Page 17DRAM EvolutionWrite-Around in ESDRAM(can second READ be this aggressive?) CommandAddressDQClockRowAddrColAddrValidDataValidDataValidDataValidDataACTREADRowAddrColAddrValidDataValidDataValidDataValidDataACTWRITEPRERegular CAS-2 SDRAM, R/W/R to same bank, rows 0/1/0CommandAddressDQClockRowAddrColAddrValidDataValidDataValidDataValidDataACT READRowAddrColAddrValidDataValidDataValidDataValidDataACT WRITEESDRAM, R/W/R to same bank, rows 0/1/0PREBankBankRowAddrColAddrValidDataValidDataValidDataACTREADPREBankColAddrValidDataValidDataValidDataValidDataREADHIGH-SPEEDMEMORYSYSTEMSSpring 2003Bruce JacobDavid WangUniversity ofMarylandLecture 11Page 18DRAM EvolutionInternal Structure of Virtual Channel Segment cache is software-managed, reduces energy$Row Decoder2Kb Segment2Kb Segment2Kb Segment2Kb SegmentBank ABank B16 ChannelsInput/OutputBufferDQsSel/Dec(segments)SenseAmps2Kbit # DQsActivatePrefetchRestoreReadWriteHIGH-SPEEDMEMORYSYSTEMSSpring 2003Bruce JacobDavid WangUniversity ofMarylandLecture 11Page 19DRAM EvolutionInternal Structure of Fast Cycle RAMReduces access time and energy/accesstRCD = 15ns tRCD = 5ns8M Array13 bitsSense Amps8M Array15 bitsSense AmpsSDRAM FCRAM(one clock)(two clocks)Row DecoderRow Decoder(8Kr x 1Kb) (?)HIGH-SPEEDMEMORYSYSTEMSSpring 2003Bruce JacobDavid WangUniversity ofMarylandLecture 11Page 20DRAM