Heading - DRAM Circuit and Architecture BasicsBullet - • OverviewBullet - • TerminologyBullet - • Access ProtocolBullet - • ArchitectureHeading - DRAM Circuit BasicsBody - DRAM CellHeading - DRAM Circuit BasicsBody - “Row” DefinedHeading - DRAM Circuit BasicsBody - Sense Amplifier IHeading - DRAM Circuit BasicsBody - Sense Amplifier II : PrechargedHeading - DRAM Circuit BasicsBody - Sense Amplifier III : Destructive ReadHeading - DRAM Access ProtocolBody - ROW ACCESSHeading - DRAM Circuit BasicsBody - “Column” DefinedHeading - DRAM Access ProtocolBody - COLUMN ACCESS IHeading - DRAM Access ProtocolBody - Column Access IIBody - note: page mode enables overlap with CASHeading - DRAM “Speed” Part IBody - How fast can I move data from DRAM cell to sense amp?Heading - DRAM “Speed” Part IIBody - How fast can I get data out of sense amps back into memory controller?Heading - DRAM “Speed” Part IIIBody - How fast can I move data from DRAM cell into memory controller?Heading - DRAM “Speed” Part IVBody - How fast can I precharge DRAM array so I can engage another RAS?Heading - DRAM “Speed” Part VBody - How fast can I read from different rows?Heading - DRAM “Speed” Summary IBody - What do I care about?Heading - DRAM “Speed” Summary IIBody - Heading - “DRAM latency”Heading - DRAM Architecture BasicsBody - PHYSICAL ORGANIZATIONBody - This is per bank … Typical DRAMs have 2+ banksHeading - DRAM Architecture BasicsBody - Read Timing for Conventional DRAMHeading - DRAM Evolutionary TreeHeading - DRAM EvolutionBody - Read Timing for Conventional DRAMHeading - DRAM EvolutionBody - Read Timing for Fast Page ModeHeading - DRAM EvolutionBody - Read Timing for Extended Data OutHeading - DRAM EvolutionBody - Read Timing for Burst EDOHeading - DRAM EvolutionBody - Read Timing for Pipeline Burst EDOHeading - DRAM EvolutionBody - Read Timing for Synchronous DRAMBody - (RAS + CAS + OE ... == Command Bus)Heading - DRAM EvolutionBody - Inter-Row Read Timing for ESDRAMHeading - DRAM EvolutionBody - Write-Around in ESDRAMCentered - (can second READ be this aggressive?)Heading - DRAM EvolutionBody - Internal Structure of Virtual ChannelCentered - Segment cache is software-managed, reduces energyHeading - DRAM EvolutionBody - Internal Structure of Fast Cycle RAMCentered - Reduces access time and energy/accessHeading - DRAM EvolutionBody - Internal Structure of MoSys 1T-SRAMDRAM MemorySystem: Lecture 2Spring 2003Bruce JacobDavid WangUniversity ofMarylandDRAM Circuit and Architecture Basics• Overview• Terminology• Access Protocol• ArchitectureStorage elementSwitching elementBit LineWord Line(capacitor)DRAM MemorySystem: Lecture 2Spring 2003Bruce JacobDavid WangUniversity ofMarylandDRAM Circuit BasicsDRAM Cell... Bit Lines...MemoryArrayRow Decoder. .. Word Lines ...DRAMStorage elementSwitching elementBit LineWord LineData In/OutBuffersSense AmpsColumn Decoder(capacitor)DRAM MemorySystem: Lecture 2Spring 2003Bruce JacobDavid WangUniversity ofMarylandRow, Bitlines and WordlinesDRAM Circuit Basics“Row” DefinedBit LinesWord Line“Row” of DRAMRow Size: 8 Kb @ 256 Mb SDRAM node4 Kb @ 256 Mb RDRAM nodeDRAM MemorySystem: Lecture 2Spring 2003Bruce JacobDavid WangUniversity ofMarylandDRAM Circuit BasicsSense Amplifier ISenseandAmplify6 Rows shown123456DRAM MemorySystem: Lecture 2Spring 2003Bruce JacobDavid WangUniversity ofMarylandDRAM Circuit BasicsSense Amplifier II : PrechargedVcc (logic 1)Gnd (logic 0)Vcc/2precharged to Vcc/2SenseandAmplify123456DRAM MemorySystem: Lecture 2Spring 2003Bruce JacobDavid WangUniversity ofMarylandDRAM Circuit BasicsSense Amplifier III : Destructive ReadSenseandAmplify123456Vcc (logic 1)Gnd (logic 0)Vcc/2WordlineDrivenDRAM MemorySystem: Lecture 2Spring 2003Bruce JacobDavid WangUniversity ofMarylandDRAM Access ProtocolROW ACCESS AKA: OPEN a DRAM Page/RowRAS (Row Address Strobe)ororACT (Activate a DRAM Page/Row)BUSMEMORYCONTROLLERCPU... Bit Lines...MemoryArrayRow Decoder. .. Word Lines ...DRAMData In/OutBuffersSense AmpsColumn DecoderDRAM MemorySystem: Lecture 2Spring 2003Bruce JacobDavid WangUniversity ofMarylandonce the data is valid on ALL of the bit lines, you can select a subset of the bits and send them to the output buffers ... CAS picks one of the bitsbig point: cannot do another RAS or precharge of the lines until finished reading the column data ... can’t change the values on the bit lines or the output of the sense amps until it has been read by the memory controllerDRAM Circuit Basics“Column” Defined“One Row” of DRAMColumn: Smallest addressable quantity of DRAM on chipSDRAM*: column size == chip data bus width (4, 8,16, 32)RDRAM: column size != chip data bus width (128 bit fixed)4 bit wide columnsSDRAM*: get “n” columns per access. n = (1, 2, 4, 8)RDRAM: get 1 column per access. #2 #3 #4 #5#0 #1* SDRAM means SDRAM and variants. i.e. DDR SDRAMDRAM MemorySystem: Lecture 2Spring 2003Bruce JacobDavid WangUniversity ofMarylandDRAM Access ProtocolCOLUMN ACCESS IREAD CommandorCAS: Column Address StrobeBUSMEMORYCONTROLLERCPU... Bit Lines...MemoryArrayRow Decoder. .. Word Lines ...DRAMData In/OutBuffersSense AmpsColumn DecoderDRAM MemorySystem: Lecture 2Spring 2003Bruce JacobDavid WangUniversity ofMarylandthen the data is valid on the data bus ... depending on what you are using for in/out buffers, you might be able to overlap a litttle or a lot of the data transfer with the next CAS to the same page (this is PAGE MODE)DRAM Access ProtocolColumn Access IInote: page mode enables overlap with CASBUSMEMORYCONTROLLERCPU... Bit Lines...MemoryArrayRow Decoder. .. Word Lines ...DRAMData In/OutBuffersSense AmpsColumn Decoder... with optional additionalCAS: Column Address StrobeData OutDRAM MemorySystem: Lecture 2Spring 2003Bruce JacobDavid WangUniversity ofMarylandNOTEDRAM “Speed” Part IHow fast can I move data from DRAM cell to sense amp? RCD (Row Command Delay)BUSMEMORYCONTROLLERCPU... Bit Lines...MemoryArrayRow Decoder. .. Word Lines ...DRAMData In/OutBuffersSense AmpsColumn DecodertRCDDRAM MemorySystem: Lecture 2Spring 2003Bruce JacobDavid WangUniversity ofMarylandDRAM “Speed” Part IIHow fast can I get data out of sense amps back into memory controller? BUSMEMORYCONTROLLERCPU... Bit Lines...MemoryArrayRow Decoder. .. Word Lines ...DRAMData In/OutBuffersSense AmpsColumn DecoderCAS: Column Address StrobetCAS aka tCLtCASL aka CASL: Column Address Strobe LatencyCL: Column Address Strobe LatencyDRAM MemorySystem: